Design and Analysis of Low Run-Time Leakage in a 13 Transistors Full Adder in 45nm Technology

Table of contents

1. I. Introduction

n this paper various 1-bit full adders are considered for leakage analysis. A 13 Transistor Full adder is designed and analysed for low leakage. Full adders considered for analysis in this paper are Complimentary MOS implementation of full adder [29], Mirror full adder [29], Transmission gate full adder [29], Manchester full adder [29], Complimentary pass transistor logic full adder, Low power Full adder, Lean integration with pass transistor full adder, 20 Transistor Transmission gate full adder, Improved 14 transistor Full adder, SERF Full adder, GDI XOR full adder, 10 transistor full adder, 9A full adder, 9B full adder, 13A full adder, 8 transistor full adder and proposed 13 transistor full adder. full adders and their implementation style at transistor level includeng the proposed full adder is as follows. CMOS 28 Transsistor Full Adder: Conventional CMOS Full Adder consists of 28 transistors as shown in fig. 1.From the following equations one can design CMOS 28 Transistor full adder circuit [29].

CO = AB + [A + B]C in (1) S = ABCi + CO(A + B + Ci ) (2)

Mirror Adder: The fig. 2. shows Mirror Adder. An improved adder circuit, also called as "Mirror Adder" [2]. This is a clever implementation of the propagate/generate/delete function when either D or G is high, CO is set VDD of Gnd, respectively. When the conditions for propagate are valid (or P is 1), the incoming carry is propagated to CO.

Figure 2: Mirror Adder [29] Complimentary pass transistor logic: The CPL Full Adder has 18 transistors [33] and is based on NMOS passtransistor logic as shown in fig. 5 Figure 12: Gate diffusion XOR Full Adder [39] Figure 13: Gate diffusion XNOR Full Adder [39] Figure 14: 10T Full Adder [41] Figure 15: 9A Full Adder [38] XNOR because there is no direct connection with ground.9B Full adder [38] is as shown in fig. 16.

13A Full Adder: The other type of 10 transistors 1-bit full adder is 13A full adder, which have better critical delay than the 10 transistors SERF full adder in all loading conditions. 13A adder [11]comes out as best when compared with respect to low power and delay. 13A adder is built using SERF XNOR and INV XNOR. The SER Full Adder: SERF adder [11] reuses charge by the energy recovering logic and hence consumes less power than non-energy recovering logic. SERF adder has no direct path to the ground, therefore power dissipation is reduced. The charge stored at the load capacitance is reapplied to the control gates. The joint effect of these two things makes the SERF adder an energy efficient design.SERF Full adder as as shown in fig. 11.

GDI XOR Full Adder: GDI [39]technique is implemented to design a high performance and low power full adder.GDI cell contains three inputs-G (common state input of NMOS and PMOS), N (input to the source or drain of NMOS) and P (input to the source or drain of PMOS). GDI XOR Full adder as shown in fig. 12.

10 Transistor Full Adder: Full adder using 10T uses more than one logic style for the implementation and it is called as Hybrid logic design style. The number of transistors count is 10. 10 Transistor Full adder [41]is as shown in fig. 14.

2. II. Simulation Results

Simulation results are presented in table I for the analysis. The table I shows the comparision of average leakage power, peak leakage power, average power and peak power in 28 Transistor full adder, Mirror, TG, Manchester, CPL, LEAP, 20T, 14T, SERF, GDI XOR, GDi XNOR, 10T, 9A,9B, 13A, 8T and proposed 13 Transistors full adders.

3. III. Conclusion

Below 70 nm technologies run-time leakage power dominates the dynamic power.So one should come up with new full adder which consumes less leakage power compared to dynamic power one such attempt is discussed in this paper.

4. IV. Acknowledgment

My sincere thanks to my guides Dr. K. Manjunathachari and Dr. K. Lalkishore for their valuable support and encouragement.

Figure 1. Table 1 :
1
Full Adders Average Leakage Peak Lekage Average Power Peak Power
28T 313.2nW 34.83uW 351.1nW 36.26uW
Mirror 288.3nW 37.48nW 317.0nW 28.75uW
TG 8.9uW 53.80uW 41.96uW 69.14uW
Manchester 9.01uW 76.24uW 42.32uW 115.32uW
CPL 27.86uW 72.52uW 39.83uW 63.03uW
LP 9.13uW 44.14uW 35.19uW 54.44uW
LEAP 29.05uW 73.88uW 38.42uW 73.75uW
20T 11.91uW 44.62uW 24.05uW 41.31uW
14T 7.04uW 18.6uW 720nW 51.89uW
SERF 2.03uW 33.31uW 14.5uW 29.55uW
GDI XOR 158nW 10.90uW 252nW 24.56uW
GDI XNOR 151.8nW 15.53uW 330.4nW 16.18uW
10T 7.83uW 31.97uW 12.55uW 31.90uW
9A 12.48uW 24.96uW 116.1nW 29.35uW
9B 85.78nW 33.95uW 12.45uW 27.39uW
13A 8.8uW 38.14uW 21.17uW 43.03uW
8T 15.76uW 34.95uW 20.36uW 31.91uW
Proposed 13T 196.4nW 17.10uW 12.67uW 52.70uW

Appendix A

Appendix A.1

Cout is designed using multiplexer.13A Full adder is as shown in fig. 17.

8 Transistor Full Adder: It is built using three multiplexers and one inverter [42]. The inverter in the circuit speeds up propagation of Cout and also provides complemented Cout signal required for generation of Sum. The xor gate is replaced by xnor gate. So the need for inverter is avoided. This reduces the transistor count to 8. The transistor level implementation of the eight transistor full adder is shown in fig. 18. Proposed 13 Transistors Full Adder: After having detail analysis we started to work by undertaking different approach so that we can reduce leakage till some extent along with increase in swing and reduce in average power. Then initially we started on investigating on output swing and came to know that by replacing A_B it is possible to increase the swing as well as decrease in leakage along with average power. It differs from complementary CMOS in that the source side of the MOS transistor is connected to an input line instead of being connected to power lines. Another important difference is that only one PTL network (either NMOS or PMOS) is sufficient to perform the logic operation. In this circuit sum is calculated from output carry. This proposed full adder resulted low leakage as well as low power as comparing with existed full adder.

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Date: 2016-01-15