Implementation of a Radial Basis Function Using VHDL
Keywords:
RBF, training algorithm, weight, block RAM, FPGA
Abstract
This paper presents the work regarding the implementation of neural network using radial basis function algorithm on very high speed integrated circuit hardware description language (VHDL). It is a digital implementation of neural network. Neural Network hardware has undergone rapid development during the last decade. Unlike the conventional von-Neumann architecture that is sequential in nature, Artificial Neural Networks (ANNs) Profit from massively parallel processing. A large variety of hardware has been designed to exploit the inherent parallelism of the neural network models. The radial basis function (RBF) network is a two-layer network whose output units form a linear combination of the basis function computed by the hidden unit
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Published
2010-07-15
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Copyright (c) 2010 Authors and Global Journals Private Limited
This work is licensed under a Creative Commons Attribution 4.0 International License.