Implementation of a Radial Basis Function Using VHDL

Authors

  • Dr. Richa kapoor

  • DEEPAK NAGARIA

  • D.C. DHUBKARYA

Keywords:

RBF, training algorithm, weight, block RAM, FPGA

Abstract

This paper presents the work regarding the implementation of neural network using radial basis function algorithm on very high speed integrated circuit hardware description language (VHDL). It is a digital implementation of neural network. Neural Network hardware has undergone rapid development during the last decade. Unlike the conventional von-Neumann architecture that is sequential in nature, Artificial Neural Networks (ANNs) Profit from massively parallel processing. A large variety of hardware has been designed to exploit the inherent parallelism of the neural network models. The radial basis function (RBF) network is a two-layer network whose output units form a linear combination of the basis function computed by the hidden unit

How to Cite

Dr. Richa kapoor, DEEPAK NAGARIA, & D.C. DHUBKARYA. (2010). Implementation of a Radial Basis Function Using VHDL. Global Journal of Computer Science and Technology, 10(10), 16–19. Retrieved from https://computerresearch.org/index.php/computer/article/view/1025

Implementation of a Radial Basis Function Using VHDL

Published

2010-07-15