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\title{Investigating the VLSI Characterization of Parallel Signed Multipliers for RNS Applications using FPGAs}
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             \author[1]{Pradeep  N}

             \author[2]{Elango  S}

             \author[3]{Sampath  P}

             \author[4]{Gayathri  K}

             \affil[1]{  Bannari Amman Institute of Technology}

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\date{\small \em Received: 16 December 2014 Accepted: 4 January 2015 Published: 15 January 2015}

\maketitle


\begin{abstract}
        


Signed multiplication is a complex arithmetic operation, which is reflected in its relatively high signal propagation delay, high power dissipation, and large area requirement. High reliability applications such as Cryptography, Residue Number System (RNS) and Digital Signal Processing (DSP)?s effective performance is mainly depend on its arithmetic circuit's performance. Trend of using Residue Number System (RNS) instead of Constrain over-whelming Binary representation is promising technique in VLSI Systems and Multiplier is the basic building block of such systems. In this paper we have considered signed Modified Baugh Wooley Multiplier and Modified Booth Encoding (MBE) Multiplier logic for analysis and synthesized on best suited application platform. Analysis has taken account of Delay, Number of Logic Element requirements; Number of Signal Transition for particular sample input and its Power Consumption were analyzed for both Modified Baugh Wooley Multiplier and Modified Booth Encoding Multiplier. Analysis of Multiplier is described in Verilog HDL and Simulated using two different simulators namely Xilinx ISIM and Altera Quartus II. Then for comparative study, both multipliers are synthesized with Xilinx Virtex 7 XCV2000T-2FLG1925 and Altera Cyclone II EP2C35F672C6 and same parameter as discussed above are also evaluated. Booth Recoding provides overall advent of 9.691% in terms of area and approximately 43 % in terms of Delay compared to Modified Baugh Wooley Multiplier implemented using FPGA Technology.

\end{abstract}


\keywords{baugh wooley multiplier, modified booth encoding (mbe), computer arithmetic, signed multiplier, verilog hdl, xilinx ise, altera quartus}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
ultiplication is a most generally used operation in wide computing systems.\par
In fact multiplication is nothing but addition since, multiplicand adds to itself multiplier number of times, gives the multiplication value between multiplier and multiplicand. But considering the fact that this kind of implementation really takes huge hardware resources and the circuit operates at utterly low speed. In order to address this so many ideas have been presented so far for the last three decades. Each one is aimed at improvement according to the requirement. One may be aimed at high clock speeds and another may be aimed for low power or less area occupation. Either way ultimate job is to come up with an efficient architecture which can address three constraints of VLSI speed, area, and power. Among three constrains, speed is the vital one which requires more attention. If we observe closely multiplication operation involves two steps one is producing partial products and adding these partial products \hyperref[b2]{[3]}.\par
Thus, the speed of a multiplier hardly depends on how fast generate the partial products and how fast we can add them together.Since the multipliers have a significant impact on the performance of the entire system, many high performance algorithms and architectures have been proposed \hyperref[b0]{[1]}\hyperref[b1]{[2]}\hyperref[b2]{[3]}\hyperref[b3]{[4]}\hyperref[b4]{[5]}\hyperref[b5]{[6]}\hyperref[b6]{[7]}\hyperref[b7]{[8]}\hyperref[b8]{[9]}\hyperref[b9]{[10]}\hyperref[b10]{[11]}\hyperref[b11]{[12]}. The very high speed and dedicated multipliers are used in pipeline and vector computers.\par
Residue Number System (RNS) reduces the delay of carry propagation, thus offering significant speed up over the conventional binary system. This characteristic is advantageous when repetitive arithmetic operations on long operands have to be performed. RNS has been adopted in the design of Digital Signal Processors (DSP) .The low power consumption of RNS compared to conventional arithmetic circuits for the implementation of Finite Impulse Response (FIR) filters inspired lot of work against it. Therefore, RNS may be an interesting candidate for building processing circuits in deep submicron technologies.\par
The rest of the paper is organized as: Section-II describes Baugh-Wooley Multiplication Section-III provides deep understanding about Modified Booth Encoding techniques, Comparative results and its analysis are exploited in Section-IV and Finally Conclusion of the paper illustrated in Section -V. 
\section[{II.}]{II.} 
\section[{Baugh Wooley Multiplier}]{Baugh Wooley Multiplier}\par
The Baugh-Wooley multiplication is one of the efficient methods to handle the sign bits and this approach has been developed in order to design regular multipliers \hyperref[b1]{[2]}, suited for 2's complement numbers.\par
Let us consider two n-bit signed numbers, X (Multiplicand) and Y (Multiplier), to be multiplied Investigating the VLSI Characterization of Parallel Signed Multipliers for RNS Applications using FPGAs2 1 1 0 2 2 n n i n i i X x x ? ? ? = = ? + ? [1] 2 1 1 0 2 2 n n i n i i Y y y ? ? ? = = ? + ? [2]\par
where the xi's and yi's are the bits in X and Y, respectively, and x n-1 and y n-1 are the sign bits. The product, P= X * Y, is then given by the following equation:P = X * Y 2 2 1 1 1 1 0 0 2 2 * 2 2 n n n i n j n i n j i j x x y y ? ? ? ? ? ? = = ? ? ? ? = ? + ? + ? ? ? ? ? ? ? ? ? ? 2 2 2 2 1 1 0 0 2 2 n n n i j n n i j i j x y x y ? ? ? + ? ? = = = + ?? 2 2 1 1 1 1 0 0 2 2 2 2 n n n i n j i n n j i j x y x y ? ? ? ? ? ? = = ? ? ? ? [3]\par
The final product can be obtained by subtracting the last two positive terms from the first two terms.\par
Instead of pursuing subtraction operation, it is possible to obtain the 2's complement of the last two terms and add all terms to get the final product. The final product (3), P=X * Y becomes:P = X * Y 2 2 2 2 1 1 0 0 2 2 2 1 1 1 1 0 0 2 1 2 2 2 2 2 2 2 2 2 n n n i j n n i j i j n n n i n j i n n j i j n n x y x y x y x y ? ? ? ? ? = = ? ? ? ? ? ? = = ? = + + + ? + ? ? ? ? [4]\par
Simple 4x4 Baugh-wooley multiplication is exhibited in figure \hyperref[fig_0]{1}.\par
Figure \hyperref[fig_0]{1} The same multiplication logic can be extended for different multiplier strength such as 4,8,16,32,64 bit-length and the efficiency is analyzed with simulation and synthesis tool .Baugh-wooley implementation require n2 AND gates and n(n-1) ADDERS as shown in figure  {\ref 2}. Figure  {\ref 2} III. 
\section[{Booth Multiplier}]{Booth Multiplier}\par
The modified-Booth algorithm \hyperref[b0]{[1]} is more preferred and extensively used for high-speed multiplier circuits. Modified Booth Multiplier is one of the different techniques for signed multiplication This multiplier order to improve the architecture, we have made 2 enhancements as in \hyperref[b13]{[14]}. The first is to use efficient Wen-Chang's Modified Booth Encoder (MBE) since it is proved as the fastest scheme to generate a partial product. a) Algorithm of the Modified Booth Multiplier Booth Multiplication consists of three \hyperref[b9]{[10]}\hyperref[b10]{[11]}\hyperref[b11]{[12]}\hyperref[b12]{[13]}\hyperref[b13]{[14]} steps:\par
1. The first step to generate the partial products; 2. The second step to add the generated partial products until the last two rows are remained; 3. The third step to compute the final multiplication results by adding the last two rows. The modified Booth algorithm reduces the number of partial products by half in the first step. We used the modified Booth encoding (MBE) scheme proposed in \hyperref[b0]{[1]}, It is known as the most efficient Booth encoding and decoding scheme. To multiply M by N using the modified Booth algorithm starts from grouping N by three bits and encoding into one of \{-2, -1, 0, 1, 2\}.Figure  {\ref 3} exhibit the general architecture of MBE. In this case, the multiplicand is offset one bit to the left to enter into the adder while for the low-order multiplicand position a 0 is added. Each time the partial product is shifted two bit positions to the right and the sign is extended to the left.
\begin{quote}
Figure 3\end{quote}
\par
During each add-shift cycle, different versions of the multiplicand are added to the new partial product depends on the equation derived from the bit-pair recoding table above. Here are some examples for understanding: Figure  {\ref 4} The new MBE recorder \hyperref[b13]{[14]} is designed in accordance to the area efficient wen-chang's Modified Booth Encoder (MBE) since it is proved to be the efficient architecture on trend, and Table \hyperref[b0]{(1)} presents the truth table of the new encoding scheme. The way of application and calculation procedure is expressed in the following examples.\par
For the ease of understanding, the main two different categories of signed multiplication are taken into consideration that is multiplication of a negative multiplicand and positive multiplier in example-1 and both negative multiplicand and multiplier in case of example-2 are clearly described for understanding.\par
Example 1: For One negative and One positive number. 
\section[{Consider -3 x 5}]{Consider -3 x 5}\par
Step-1: binary conversion and 2's complement\par
Step-2: Multiplication by Modified booth recoding Example 2: For Both Negative Numbers. 
\section[{Consider -3 x -4}]{Consider -3 x -4}\par
Step-1: Binary conversion and 2's complement\par
Step-2: Multiplication by Modified booth recoding Once the partial products are generated then the addition process is very similar to the array multiplier.\par
IV. 
\section[{Results and Analysis}]{Results and Analysis}\par
The Multiplier were taken for analysis was described using structural Verilog HDL and synthesized to produce a gate level net list using two different synthesizer namely Xilinx ISE Design Suite 14.  
\section[{c) Power Analysis}]{c) Power Analysis}\par
Power Evaluation of the design done at various levels such as Total Thermal power Dissipation (mWmilli Watt's), Core Dynamic Thermal power Dissipation (mW), core static Thermal power Dissipation (mW), I/O Thermal Power Dissipation(mW). Among the various power levels dynamic power varies with design to design it decides the efficient architecture.\par
Dynamic Power Requirement of the design is decided based on number of signal transition (or) activity during simulation time. Here analysis has been made using Power Play Power Analyzer from Altera. Power Analyzer required an input file of Signal Activities and Value Changed Dump (VCD) File to evaluate the power of the design. Here we have measure the signal activities count for 20 different Samples for 100ns simulation and the same sample is forced for other design also in order to evaluate the exact power difference between the design. power Analysis with powerplay analyzer tool for 4 x 4 bit shows 46.90\% Modified Booth consume less than Baugh-wooley Multiplier and found consistence for all strength.  
\begin{quote}
Figure 5\end{quote}
\par
The Xilinx Simulation result for booth-32 x 32 bit is exhibited below in the Figure  {\ref 5}, and then the structure level port-map model is synthesized as Gate-level Netlist for signal Transition calculation. Modified Booth's 64 x 64 bit simulation result on Altera Quartus-II is illustrated in the Figure \hyperref[fig_2]{6}, and then synthesis summary is depicted inFigure7-11.     \begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-3.png}
\caption{\label{fig_1}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Figure 6 Global}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{9}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Figure 9 -}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{789}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Figure 7 Figure 8 Figure 9}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{10}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Figure 10}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{11}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Figure 11 V}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-9.png}
\caption{\label{figure9}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.11258278145695365\textwidth}P{0.18013245033112582\textwidth}P{0.09288079470198675\textwidth}P{0.26175496688741723\textwidth}P{0.20264900662251656\textwidth}}
Multipliers\tabcellsep Multiplier\tabcellsep No.\tabcellsep \multicolumn{2}{l}{Altera Cyclone II}\\
Strength\tabcellsep Name\tabcellsep of\tabcellsep \multicolumn{2}{l}{EP2C35F672C6}\\
\tabcellsep \tabcellsep IOBs\tabcellsep \tabcellsep \\
\tabcellsep \tabcellsep \tabcellsep No. of\tabcellsep Delay\\
\tabcellsep \tabcellsep \tabcellsep Logic\tabcellsep (ns)\\
\tabcellsep \tabcellsep \tabcellsep Elements\tabcellsep \\
\tabcellsep \tabcellsep \tabcellsep Required\tabcellsep \\
4x4\tabcellsep BAUGH\tabcellsep 16\tabcellsep 30\tabcellsep 15.650\\
\tabcellsep BOOTH\tabcellsep 16\tabcellsep 28\tabcellsep 10.173\\
8x8\tabcellsep BAUGH\tabcellsep 32\tabcellsep 164\tabcellsep 36.994\\
\tabcellsep BOOTH\tabcellsep 32\tabcellsep 150\tabcellsep 25.082\\
16x16\tabcellsep BAUGH\tabcellsep 64\tabcellsep 698\tabcellsep 99.377\\
\tabcellsep BOOTH\tabcellsep 64\tabcellsep 538\tabcellsep 42.826\\
32x32\tabcellsep BAUGH\tabcellsep 128\tabcellsep 2,874\tabcellsep 325.172\\
\tabcellsep BOOTH\tabcellsep 128\tabcellsep 2,284\tabcellsep 87.473\\
64x64\tabcellsep BAUGH\tabcellsep 256\tabcellsep 10,122\tabcellsep 956.214\\
\tabcellsep BOOTH\tabcellsep 256\tabcellsep 9,542\tabcellsep 189.886\end{longtable} \par
 
\caption{\label{tab_0}Table 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3} \par 
\begin{longtable}{P{0.11888111888111888\textwidth}P{0.1902097902097902\textwidth}P{0.09807692307692308\textwidth}P{0.2526223776223776\textwidth}P{0.1902097902097902\textwidth}}
Multipliers\tabcellsep Multiplier\tabcellsep No.\tabcellsep \multicolumn{2}{l}{Xilinx Virtex7}\\
Strength\tabcellsep Name\tabcellsep of\tabcellsep \multicolumn{2}{l}{XCV2000T-}\\
\tabcellsep \tabcellsep IOBs\tabcellsep \multicolumn{2}{l}{2FLG1925}\\
\tabcellsep \tabcellsep \tabcellsep No. of\tabcellsep Delay\\
\tabcellsep \tabcellsep \tabcellsep Slice\tabcellsep (ns)\\
\tabcellsep \tabcellsep \tabcellsep LUTs\tabcellsep \\
\tabcellsep \tabcellsep \tabcellsep Required\tabcellsep \\
4x4\tabcellsep BAUGH\tabcellsep 16\tabcellsep 20\tabcellsep 15.91\\
\tabcellsep BOOTH\tabcellsep 16\tabcellsep 18\tabcellsep 10.14\\
8x8\tabcellsep BAUGH\tabcellsep 32\tabcellsep 104\tabcellsep 55.93\\
\tabcellsep BOOTH\tabcellsep 32\tabcellsep 96\tabcellsep 22.15\\
16x16\tabcellsep BAUGH\tabcellsep 64\tabcellsep 452\tabcellsep 191.84\\
\tabcellsep BOOTH\tabcellsep 64\tabcellsep 354\tabcellsep 40.87\\
32x32\tabcellsep BAUGH\tabcellsep 128\tabcellsep 1851\tabcellsep 670.46\\
\tabcellsep BOOTH\tabcellsep 128\tabcellsep 1595\tabcellsep 81.19\\
64x64\tabcellsep BAUGH\tabcellsep 256\tabcellsep 7392\tabcellsep 1838.32\\
\tabcellsep BOOTH\tabcellsep 256\tabcellsep 6480\tabcellsep 159.28\end{longtable} \par
  {\small\itshape [Note: A]} 
\caption{\label{tab_1}Table 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4} \par 
\begin{longtable}{P{0.0528030303030303\textwidth}P{0.09015151515151515\textwidth}P{0.145530303030303\textwidth}P{0.17128787878787877\textwidth}P{0.19446969696969696\textwidth}P{0.07083333333333333\textwidth}P{0.12492424242424242\textwidth}}
\tabcellsep \tabcellsep \tabcellsep \multicolumn{3}{l}{Altera Cyclone II EP2C35F672C6}\tabcellsep \\
Multipliers Strength\tabcellsep Multiplier Name\tabcellsep Number Signal Transition during simulation for 100ns\tabcellsep Total Thermal Power Dissipation (mW)\tabcellsep \multicolumn{2}{l}{Power estimation Dynamic Core Thermal Dissipation (mW) Core Static Thermal power Dissipation (mW)}\tabcellsep I/O Thermal power Dissipation (mW)\\
4x4\tabcellsep BAUGH BOOTH\tabcellsep 1857 986\tabcellsep 169.92 166.13\tabcellsep 1.13 1.01\tabcellsep 80.12 80.01\tabcellsep 86.67 86.59\\
8x8\tabcellsep BAUGH BOOTH\tabcellsep 20911 10291\tabcellsep 223.47 223.39\tabcellsep 4.81 5.28\tabcellsep 80.30 80.30\tabcellsep 138.36 138.30\\
16x16\tabcellsep BAUGH BOOTH\tabcellsep 498261 51942\tabcellsep 351.24 345.25\tabcellsep 27.12 19.86\tabcellsep 80.74 80.72\tabcellsep 243.39 244.67\\
32x32\tabcellsep BAUGH BOOTH\tabcellsep 9606019 469336\tabcellsep 642.20 601.67\tabcellsep 115.05 82.31\tabcellsep 81.75 81.61\tabcellsep 445.40 437.74\\
64x64\tabcellsep BAUGH BOOTH\tabcellsep 19212038 1877344\tabcellsep 1302.34 1278.88\tabcellsep 331.53 360.30\tabcellsep 83.13 83.24\tabcellsep 887.68 836.34\end{longtable} \par
 
\caption{\label{tab_2}Table 4 :}\end{figure}
 			\footnote{© 2015 Global Journals Inc. (US) 1} 			\footnote{© 2015 Global Journals Inc. (US)} 		 		\backmatter  			 			 			  				\begin{bibitemlist}{1}
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\end{document}
