Energy Efficient Branch and Bound based On-Chip Irregular Network Design

Authors

  • Kalpana Jain

  • Naveen Choudhary

Keywords:

network on chip, shortest path, branch and bound, routing

Abstract

Here we present a technique which construct the topology for heterogeneous SoC, (Application Specific NoC) such that total Dynamic communication energy is optimized. The topology is certain to satisfy the constraints of node degree as well the link length. We first layout the topology by finding the shortest path between traffic characteristics with the branch and bound optimization technique. Deadlock is dealt with escape routing using Spanning tree. Investigation outcome show that the proposed design methodology is fast and achieves significant dynamic energy gain.

How to Cite

Kalpana Jain, & Naveen Choudhary. (2014). Energy Efficient Branch and Bound based On-Chip Irregular Network Design. Global Journal of Computer Science and Technology, 14(C4), 7–11. Retrieved from https://computerresearch.org/index.php/computer/article/view/113

Energy Efficient Branch and Bound based On-Chip Irregular Network Design

Published

2014-03-15