Abstract

In the last decade, Networks-on-Chips became the leading edge technology due to the growing requirements of electronic systems. Basically, NoC is an advancement of bus interconnect technology. The challenge is to interconnect existing components such as processors, controllers, and memory arrays in such a way that there is an optimal utilization of communication resources necessitating optimization of the various dominant factors like energy/power consumption, interconnection delay, latency, throughput, etc. In this paper, we focused on the evolution of NoC. Then we studied and have shown through an example that when application specific long-range links are inserted among the tiles whose communication frequencies are high, there is a reduction in the average packet latency and an energy efficient architecture is build up with high throughput. We also discussed the turn model which is deadlock free and the energy model for NoC.