@incollection{,
	
					
					
					2710E5689EC6828C384E3AC79A9B4E20
				,
	author={{AbdulraqebAlnabihi} and {Guangdong University of Technology}},
	journal={{Global Journal of Computer Science and Technology}},
	journal={{GJCST}}0975-41720975-435010.34257/gjcst,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}152132
}

@incollection{b0,
	
	
		,
	title={{}}
		,
	author={{
			NaokiFujieda
		} and {
			TakefumiMiyoshi
		} and {
			KenjiKise
		}}
		
		
	
	
		,
	journal={{SimMips A MIPS System Simulator}}
		
	

}

@book{b1,
	
	
		,
	title={{MIPS® Architecture For Programmers Volume III-A: Introduction to the MIPS32® Architecture}}
		
	

}

@book{b2,
	
	
		,
	title={{MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS32® Architecture}}
		
	

}

@book{b3,
	
	
		,
	title={{MIPS® Architecture For Programmers Volume II-A: Introduction to the MIPS32® Architecture}}
		
	

}

@book{b4,
	
	
		,
	title={{}}
		,
	author={{
			Linux Porting Guide
		}}
		
		
	

}

@book{b5,
	
	
		,
	title={{Simple Scalar Simulator Toolset}}
		
		
	

}

@incollection{b6,
	
	
		,
	title={{Fading reduction by aperture averaging and spatial diversity in optical wireless systems}}
		,
	author={{
			MAKhalighi
		} and {
			NSchwartz
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			NAitamer
		} and {
			SBourennane
		}}
		
		
		
	
	
		,
	journal={{Journal of Optical Communications and Networking}}
		
			1
			
			,
	year={2009}
		
	
	,
	note={IEEE/OSA}

}

@incollection{b7,
	
	
		,
	title={{Performance evaluation of optically preamplified digital pulse position modulation turbulent freespace optical communication systems}}
		,
	author={{
			AOAladeloba
		} and {
			AJPhillips
		} and {
			MSWoolfson
		}}
		
		
	
	
		,
	journal={{IET Optoelectronics}}
		
			6
			
			,
	year={February 2012}
		
	

}

@incollection{b8,
	
	
		,
	title={{Aperture averaging of optical scintillations: power fluctuations and the temporal spectrum}}
		,
	author={{
			LCAndrews
		} and {
			RLPhillips
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			CYHopen
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	journal={{Waves Random Media}}
		
			10
			
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	year={2000}
		
	

}

@incollection{b9,
	
	
		,
	title={{Understanding the performance of freespace optics}}
		,
	author={{
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			EKorevaar
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			JSchuster
		} and {
			HAWillebrand
		}}
		
		
		
	
	
		,
	journal={{Journal of Optical Networking}}
		
			2
			
			,
	year={June 2003}
		
	

}

@incollection{b10,
	
	
		,
	title={{Pointing error effects on free-space optical communication links in the presence of atmospheric turbulence}}
		,
	author={{
			DKBorah
		} and {
			DGVoelz
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	journal={{Journal of Lightwave Technology}}
		
			27
			
			,
	year={2009}
		
	

}

@incollection{b11,
	
	
		,
	title={{Outage capacity optimization for free-space optical links with pointing errors}}
		,
	author={{
			AAFarid
		} and {
			SHranilovic
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	journal={{Journal of Lightwave Technology}}
		
			25
			
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	year={2007}
		
	

}

@book{b12,
	
	
		,
	author={{
			HGSandalidis
		} and {
			TATsiftsis
		} and {
			GKKaragiannidis
		} and {
			MUysal
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@incollection{b13,
	
	
		,
	title={{FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores Within a Canonical Superscalar Template}}
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	author={{
			NKChoudhary
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			SNavada
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		} and {
			ERotenberg
		}}
		
		
		
		
		
		
		
		
		
	
	
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				the 38th Annual International Symposium on Computer Architecture
		
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	publisher={ACM}
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	year={2011. 2000064.2000067}
		
	

}

@incollection{b14,
	
	
		,
	title={{strong atmospheric turbulence channels with pointing errors}}
	
	
		,
	journal={{IEEE Communications Letters}}
		
			12
			
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	year={2008}
		
	

}

@incollection{b15,
	
	
		,
	title={{Power penalty for burst mode reception in the presence of interchannel crosstalk}}
		,
	author={{
			AJPhillips
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	journal={{IET Optoelectronics}}
		
			1
			
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	year={2007}
		
	

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	year={1984}
			2
		
	
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	note={Mathematical topics in telecommunications}

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	author={{
			ITMonroy
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	title={{Crosstalk in WDM communication networks}}
				Norwell, Massachusetts, USA
		
			,
	publisher={Kluwer Academic Publishers}
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	year={2002}
		
	

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@incollection{b18,
	
	
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	title={{Improved error probability evaluation methods for direct detection optical communication systems}}
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@incollection{b19,
	
	
		,
	title={{Mishra Prabhat, DuttNikil, Nicolau Alex. Specification of Hazards, Stalls, Interrupts, and Exceptions in Expression}}
		,
	author={{
			LF BRibeiro
		} and {
			JR FDa Rocha
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			JLPinto
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		#01-05
	
	
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			Dept. of Information and Computer Science, University of California
		
	
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}

@book{b20,
	
	
		,
	title={{Implementing Precise Interruptions in Pipelined RISC Processors}}
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	author={{
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			EmnettFrank
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	year={1993}
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	publisher={IEEE}
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@book{b21,
	
	
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	title={{Implementation Mechanism of Precise Interrupts in Microprocessors, High Performance Computing Technology}}
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	author={{
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	title={{New precise interrupt mechanism based on backup-buffer. Computer Engineering and Applications}}
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	author={{
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			Sheng-Bing
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			Xu-Bang
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	year={2007}
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@incollection{b23,
	
	
		,
	title={{Design of Instruction Decoder for Use in China for an Embedded MPU}}
		,
	author={{
			Liu Shibin
		} and {
			FanGaodeyuan
		} and {
			Xiaoya
		}}
		
		
	
	
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	journal={{Journal of Northwestern Polytechnic University}}
		
			19
			1
			
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	year={2001}
		
	

}

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	title={{The IBM systeml360 Model 91 : Machine philosophy and instruction handling}}
		,
	author={{
			DWAnderson
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			F1Sparacio
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			FMTomasulo
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	journal={{IBM 1. Res. Develop}}
		
			11
			
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	year={Jan. 1967}
		
	

}

@incollection{b25,
	
	
		,
	title={{Implementing precise interrupts in pipelined processors}}
		,
	author={{
			EOzer
		} and {
			SWSathaye
		} and {
			KNMenezes
		} and {
			SBanerjia
		} and {
			MDJennings
		} and {
			TMConte
		}}
		
		
		
		
		
	
	
		,
	booktitle={{Proceedings. 1998 International Conference on Digital Object Identifier: IO.l109IPACT.l998.727184 Publication Year}}
				,
	editor={
			.ESmith
			ARPleszkun
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		1998 International Conference on Digital Object Identifier: IO.l109IPACT.l998.727184 Publication YearPage(s
		
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	year={1998. 1998. May 1988}
			28
			
		
	
	,
	note={A fast interrupt handling scheme for VLIW processors}

}

@incollection{b26,
	
	
		,
	title={{Checkpoint Repair for Out-of-Order Execution Machines}}
		,
	author={{
			W-MWHwu
		} and {
			YNPatt
		}}
		
	
	
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	journal={{IEEE Trans. Computers}}
		
			36
			l2
			522
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	year={Dec. 1987}
		
	

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@incollection{b27,
	
	
		,
	title={{A decoupled KILO-instruction processor}}
		,
	author={{
			MPericas
		} and {
			ACristal
		} and {
			RGonzalez
		} and {
			DAJimenez
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			MValero
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		,
	booktitle={{High-Performance Computer Architecture}}
				
			,
	year={2006}
		
	
	,
	note={The Twelfth International Symposium on. On page(s}

}

@book{b28,
	
	
		,
	title={{}}
		,
	author={{
			DominicSweetman
		} and {
			MipsSee
		} and {
			Run
		}}
		
		
		
			,
	year={2002}
			,
	publisher={Academic Press}
		
	

}

@book{b29,
	
	
		,
	title={{Computer Organization and Design: The Hardware/Software Interface}}
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	author={{
			JohnLDavid A Patterson
		} and {
			Hennessy
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	year={1998}
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	publisher={Morgan Kaufmann Publishers, Inc}
		
	

}

@book{b30,
	
	
		,
	title={{Fundamentals of Digital Logic with VHDL Design}}
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	author={{
			StephenBrown
		} and {
			Zvonkovranesic
		}}
		
		
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	year={2000}
			,
	publisher={McGraw-Hill}
		
	

}

@incollection{b31,
	
	
		,
	title={{Altera university program-Learning through innovation}}
		,
	author={{
			ZhuZiyu
		} and {
			LiYamin
		}}
		
	
	
		,
	journal={{Altera Corporation}}
		
			2011
			,
	year={2005 35}
		
		
			CPU Chip Logic Design. Tsinghua University Press
		
	

}

@incollection{b32,
	
	
		,
	title={{The undergraduate curriculum in computer architecture}}
		,
	author={{
			AClements
		}}
		
	
	
		,
	booktitle={{Available}}
				
			,
	year={May-Jun. 2000}
			20
			
		
	

}

@incollection{b33,
	
	
		,
	title={{CAL2: Computer aided learning in computer architecture laboratory}}
		,
	author={{
			JDjordjevic
		} and {
			BNikolic
		} and {
			TBorozan
		} and {
			AMilenkovie
		}}
		
		
		
	
	
		,
	journal={{Comput. Appl. Eng. Educ}}
		
			16
			
			,
	year={2008}
		
	

}

@incollection{b34,
	
	
		,
	title={{A survey and evaluation of simulators suitable for teaching courses in computer architecture and organization}}
		,
	author={{
			BNikolic
		} and {
			ZRadivojevic
		} and {
			JDjordjevic
		} and {
			VMilutinovic
		}}
		
		
		
	
	
		,
	journal={{IEEE Trans. Educ}}
		
			52
			4
			
			,
	year={Nov. 2009}
		
	

}

@incollection{b35,
	
	
		,
	title={{BZK.SAU: Implementing a hardware and software-based computer architecture simulator for educational purpose}}
		,
	author={{
			HOztekin
		} and {
			FTemurtas
		} and {
			AGulbag
		}}
		
		
	
	
		,
	booktitle={{Proc. 2nd Int. Conf}}
				2nd Int. Conf
		
			,
	year={2010}
			
		
	

}

@incollection{b36,
	
	
		,
	title={{80 # address of data[0] 2: call : jal sum # call function 3: dslot1: addi r5, r0, 4 # DELAYED SLOT(DS) 4: return: sw r2, 0(r4) # store result 5: lw r9, 0(r4) # check sw 6: sub r8, r9}}
		,
	author={{
			VGustin
		} and {
			PBulic
		}}
		
		2006. 0: main :lui r1, 0 # address of data[0] 1: ori r4
	
	
		,
	booktitle={{r4 # sub: r8 ? r9 -r4 7: addi r5, r0, 3 # counter 8: loop: addi r5, r5, -1 # counter -1 9: ori r8, r5, 0xffff # zero-extended : 0000ffff A: xori r8, r8, 0x5555#zero-extended : 0000aaaa B: addi r9, r0, -1 # sign-extended :ffffffff C: andi r10, r9, 0xffff # zero-extended : 0000ffff D: or r6, r10, r9 # or: ffffffff E: xor r8, r10, r9 # xor: ffff0000 F: and r7, r10, r6 # and: 0000ffff 10: beq r5, r0, shift # if r5 =0, goto shift 11: dslot2:nop # DS 12: j loop2 # jump loop2 13: dslot3: nop # DS 14: shift: addi r5, r0, -1 # r5 = ffffffff 15: sll r8, r5, 15 # <<15 = ffff8000 16: sll r8, r8, 16 # <<16 = 80000000 17: sra r8}}
				
			14
			
		
	
	,
	note={Learning computer architecture concepts with the FPGA-based. r8, 16 # >>16 = ffff8000(arith) 18: srl r8, r8, 15 # >>15 = 0001ffff(logic) 19: finish: j finish # dead loop 20: dslot4: nop # delay slot}

}

@book{b37,
	
	
		,
	title={{Appendix B Interrupt and Exception Verification Program 0: reset : j start # entry on reset 1: nop 2:EXC_BASE: mfc0 r26, C0_CAUSE # read cp0 Cause reg 3: andi r27, r26, 0xc # get ExcCode, 2 bits here 4: lw r27, j_table (r27) # get address from table 5: nop 6: jr r27 # jump to that address 7: nop c: int_entry: nop #0.interrupt handler deal with interrupt here d: eret # return from interrupt e: nop f:sys_entry: nop # SysCall handler 10: epc_plus4: mfc0 r26, C0_EPC # get EPC 11: addi r26, r26, 4 #EPC + 4 12: mtc0 r26, C0_EPC #EPC ? EPC +4 13: eret #return from exception 14: nop 15: uni_entry: nop 16: j epc_plus4 #return 17: nop 1a: ovf_entry: nop #overflow handler 1b: j epc_plus4 #return 1c: nop 1d: start: addi r8, r0, 0xf # IM}}
				
	
	,
	note={3:0] ? 1111 1e: mtc0 r8, C0_STATUS # exc/intr enable}

}