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\title{Design and Implementation of Data Scrambler \& Descrambler System using VHDL}
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\begin{document}

             \author[1]{Naina  Randive}

             \affil[1]{  Sant Gadge Baba Amaravati University}

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\date{\small \em Received: 10 December 2014 Accepted: 5 January 2015 Published: 15 January 2015}

\maketitle


\begin{abstract}
        


Multimedia data security is very important for multimedia commerce on the internet and real time data multicast. An striking solution for encrypting data with adequate message security at low cost is the use of Scrambler/Descrambler. Scramblers are necessary components of physical layer system standards besides interleaved coding and modulation. Scramblers are well used in modern VLSI design especially those are used in data communication system either to secure data or re-code periodic sequence of binary bits stream. However, it is necessary to have a descrambler block on the receiving side while using scrambling data in the transmitting end to have the actual input sequence on the receiving end. Scrambling and De-scrambling is an algorithm that converts an input string into a seemingly random string of the same length to avoid simultaneous bits in the long format of data. Scramblers have accomplish of uses in today's data communication protocols. On the other hand, those methods that are theoretical proposed are not feasible in the modern digital design due to many reasons such as slower data rate, increasing information, circuit hazards, uncountable hold-up etc. Therefore it is requisite for the modern digital design to have modified architecture to meet the required goal. We will recommend here modified scrambler design which is perfectly suitable for any industrial design.

\end{abstract}


\keywords{scrambler, descrambler, VHDL, and FPGA.}

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\let\tabcellsep& 	 	 		 \par
Abstract-Multimedia data security is very important for multimedia commerce on the internet and real time data multicast. An striking solution for encrypting data with adequate message security at low cost is the use of Scrambler/Descrambler. Scramblers are necessary components of physical layer system standards besides interleaved coding and modulation. Scramblers are well used in modern VLSI design especially those are used in data communication system either to secure data or re-code periodic sequence of binary bits stream. However, it is necessary to have a descrambler block on the receiving side while using scrambling data in the transmitting end to have the actual input sequence on the receiving end. Scrambling and De-scrambling is an algorithm that converts an input string into a seemingly random string of the same length to avoid simultaneous bits in the long format of data. Scramblers have accomplish of uses in today's data communication protocols. On the other hand, those methods that are theoretical proposed are not feasible in the modern digital design due to many reasons such as slower data rate, increasing information, circuit hazards, uncountable hold-up etc. Therefore it is requisite for the modern digital design to have modified architecture to meet the required goal. We will recommend here modified scrambler design which is perfectly suitable for any industrial design.\par
Keywords: scrambler, descrambler, VHDL, and FPGA. 
\section[{I. INTRODUCTION}]{I. INTRODUCTION}\par
n telecommunications, a scrambler is a device that transposes or inverts signals or otherwise encodes a message at the transmitter to make the message unintelligible at a receiver not equipped with an appropriately set descrambling device. while encryption usually refers to operations carried out in the digital domain, scrambling typically refers to operations carried out in the analog domain. Scrambling is consummate by the addition of components to the original signal or the changing of some important component of the original signal in order to make extraction of the original signal complex .To improve the degree of data security in a conventional Scrambler the number of stages of the shift register needs to be enhanced. This conversely increases error propagation. A uncomplicated method for ensuring security is to encrypt the data. The pseudonoise (PN) key generation is of paramount importance Author ? ?: Dept. of Electronics and Telecommunications Dept. of Electronics and Telecommunications P.R. Pote (Patil) college of Engineering and, Management, Amravati, India. e-mails: naina0689@gmail.com, gauri.borkhade@gmail.com for any secure communication system. PN sequences base on Linear Feedback Shift Registers (LFSR) and non linear combination based implementations are simplest to give moderate level of security. Chaos base encryption techniques have proved fruitful, but complexity of such systems is important. The complex system generated is used to scramble incoming plain text. At the receiving end, the same code be generated and successfully used to decrypt the transmitted data. The ease of the circuit along with the complexity of the generated codes makes the circuit striking for secure message communication applications. 
\section[{II. PROPOSED WORK}]{II. PROPOSED WORK}\par
The entire operation is proposed using Modelsim and Xilinx blocks goes through three phases.  Descrambler is performed in order XOR the 8bit crypt word (D0-D7) character with the 8-bit output of the LFSR. An output of the LFSR is XOR with crypto word of the data to be processed. The LFSR and data register are then consecutively advanced and the output processing is repeated for D1 through D7. 
\section[{c) Overview of Scrambler and Descrambler}]{c) Overview of Scrambler and Descrambler}\par
In the transmitter, a pseudorandom cipher sequence is added (modulo 2) to the data (or control) sequence to produce a scrambled data (or control) sequence.\par
In the receiver, the same pseudorandom cipher sequence is subtracted (modulo 2) from the scrambled data (or control) sequence to recover the transmitted data (or control) sequence, as illustrated in figure.          A new modified scheme for complex PN-code based data scrambler and descrambler has been presented. A scrambler \& descrambler accepts information in intelligible form and through intellectual transformation assure data quality with fastest rate without any error or dropping occurrence. We used our proposed and modified design in our present universal serial bus architecture. Moreover, this current design is very efficient, more securable, high speed, low power and lower area used \& it has lots of scope to improved. 
\section[{V. ACKNOWLEDGMENT}]{V. ACKNOWLEDGMENT}\par
I have taken efforts in this project. Though it would not have been possible without the kind support and help of many individuals and organizations. I would like to make bigger my sincere thanks to all of them. I am highly indebted to Prof .G. P. Borkhade for their guidance and constant supervision as well as for providing necessary information regarding the project \& also for their support in completing the project.\par
I would like to convey my pleasure towards my guide \& member of Electronics and Telecommunication Engineering for their kind co-operation and encouragement which help me in completion of this project.\par
I would like to express my special gratitude and thanks to institute persons for giving me such attention and time. My thanks and appreciations also go to my colleague in developing the project and people who have willingly helped me out with their abilities.\begin{figure}[htbp]
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 			\footnote{© 2015 Global Journals Inc. (US)} 			\footnote{© 2015 Global Journals Inc. (US) 1} 		 		\backmatter  			  				\begin{bibitemlist}{1}
\bibitem[Liu et al. (2013)]{b6}\label{b6} 	 		\textit{A Study of Reconstruction of Linear Scrambler using Dual Words of Channel Encoder},  		 			Xiao-Bei Liu 		,  		 			Soo Ngee Koh 		,  		 			Chee-Cheon Chui 		,  		 			Xin-Wen Wu 		.  		March 2013.  	 
\bibitem[Davinder Pal and Sharma ()]{b1}\label{b1} 	 		\textit{Data scrambler of ultrawide band communication system},  		 			Davinder Pal 		,  		 			Sharma 		.  		2013.  	 
\bibitem[Kumar and Kumar (2014)]{b5}\label{b5} 	 		\textit{Design and implementation of Logical Scrambler Architecture for OTN Protocol},  		 			Hethan Kumar 		,  		 			Praveen Kumar 		,  		 			Y G 		,  		 			Dr 		.  		April 2014. 3.  	 
\bibitem[Sharma and Singh ()]{b4}\label{b4} 	 		‘DSP based implementation of scrambler for 56Kbps modem’.  		 			D P Sharma 		,  		 			J Singh 		.  	 	 		\textit{Signal Processing -An International Journal}  		2010. 4 p. .  	 
\bibitem[Indurtial Modified Digital scrambler and descrambler system Rajib Imranand Monirul Islam ()]{b0}\label{b0} 	 		‘Indurtial Modified Digital scrambler and descrambler system’.  	 	 		\textit{Rajib Imranand Monirul Islam}  		2013.  	 
\bibitem[Sharma and Singh ()]{b3}\label{b3} 	 		\textit{Simulation and spectral analysis of the scrambler for 56Kbps modem. The Journal of Signal Processing Systems},  		 			D P Sharma 		,  		 			J Singh 		.  		2012. 67 p. .  	 
\bibitem[Bhat et al. ()]{b2}\label{b2} 	 		\textit{VHDL modeling and simulation of data scrambler and descrambler for secure data communication},  		 			G M Bhat 		,  		 			M Mustafa 		,  		 			Shabir Ahmad 		,  		 			Javaid Ahmad 		.  		2009.  	 
\end{bibitemlist}
 			 		 	 
\end{document}
