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\begin{document}

             \author[1]{Samta  Jain}

             \author[2]{Vaishali  Sodani}

             \author[3]{Naveen  Choudhary}

             \affil[1]{  College of Technology and Engineering, Udaipur}

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\date{\small \em Received: 13 December 2015 Accepted: 2 January 2016 Published: 15 January 2016}

\maketitle


\begin{abstract}
        


On-chip communication, modular, scalable packet-switched micro-network of interconnects, generally known as Network-on-Chip (NoC) architecture can be designed as regular or application-specific (irregular) network topologies. Application specific custom network topologies are advantageous in terms of optimized design according to given performance metrics and regular network topologies are advantageous in terms of its modularity, lower design time and efforts required and thus are suitable for mass production. So to offer the advantages of both the topologies this paper proposes a methodology to augment the regular topology according to the application characteristics. The experimental results demonstrate that the proposed methodology can reduce dynamic communication energy consumption by on average of 32.79% and reduction in average per flit latency by on average of 16.22% over regular 2D NoC architecture.

\end{abstract}


\keywords{network-on-chip, application specific topology, interconnection network, dynamic communication energy.}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
etwork-on-Chip designs consist of a number of interconnected devices (e.g. general or special purpose processors, peripherals, memories etc.) where communication between these system modules is achieved by sending packets over an interconnection network. Packets are transported from one to another module via the interconnection networks \hyperref[b0]{[1]}. Thus, the interconnections among multiple cores on a chip have a significant impact on communication and performance of the chip design in terms of dynamic energy consumption, latency, throughput etc. So topology selection is an important choice in the design of NoC and in Network on Chip topology design is one of the significant factor that affects the net delay of the system and the dynamic communication energy of the system. Topological parameters, like hop count, wiring layout are closely related to the performance and power dissipation of a network \hyperref[b15]{[13]}. In other words, it can be said that the NoC performance can be greatly affected by the underlying topology and the routing function followed by the communication cores.\par
NoC architecture can be designed as regular or application specific network topology. Application-specific network topologies are designed to make the system more application centric \hyperref[b1]{[2]}. As a result, the performance objectives such as power consumption, latency, area of the chip, number of routers in the system can be optimized effectively with the given design constraints \hyperref[b2]{[3]}. However the loss of modularity in application-specific NoC generally leads to increased time-to-market in comparison to the modular generic standard NoC topologies.\par
Regular topologies like 2D mesh are more structured and built not considering much about the application characteristics. A regular NoC topology assumes a homogeneous distribution of routers, which leads among others to lower design time and cost. Therefore regular NoC topologies are suitable for mass production due to lower design cost and effort required. Additionally, regular topologies are highly reusable and impose the minimum re-design effort, in case they are employed to different applications.\par
However, due to the lack of fast paths between remotely situated nodes and many hops between different communicating nodes regular topology architectures for a given routing methodology may suffer from long packet latencies and higher communication power dissipation. Although the regular structure significantly address the implementation issues, such as floor planning, unequal lengths of wire, hence results in poorly controlled electrical parameters.\par
In order to meet the communication requirements, accelerate time-to-market and cut down the communication energy consumption, there is a great need to find new design alternatives of customizing the regular architectures as per the communication requirements. We therefore focused our research on exploring and finding an efficient methodology to tailor the regular 2D mesh topology so that the dynamic communication energy can be optimized. The methodology will optimize the dynamic communication energy consumption by reducing the hop count or by reducing the number of short links according to the traffic characteristics of the application for a given routing function. Tailoring the regular topology shall reduce the design time in comparison to the design of application specific NoC from stretch with reasonable performance advantages.1 Year 2016 ( ) E Samta Jain ? , Vaishali Sodani ? \& Naveen Choudhary ?\par
In \hyperref[b3]{[4]}, the authors introduce additional random links to the mesh and torus network and investigate the performance of these networks. In \hyperref[b4]{[5]}, authors present a methodology to automatically synthesize an architecture where a few application-specific long-range links are introduced on a regular mesh network. Drawing inspiration from such work this paper proposes the methodology to insert energy conscious shortcut links with practical design constraints such as link length, port constraints. The proposed design also strives to add minimum number of shortcuts so as not to distinguish the original design in terms of area and floor-planning.\par
In section 2, NoC communication energy and routing functions are discussed. In section 3, the proposed methodology is given. In the next section, the experimental results are discussed and in the last section the conclusion is presented based on the results. 
\section[{II.}]{II.} 
\section[{Noc Communication Energy and Routing Function a) Dynamic Communication Energy Model}]{Noc Communication Energy and Routing Function a) Dynamic Communication Energy Model}\par
The dynamic communication energy model \hyperref[b7]{[7]} for the network on chip can be defined as:E bit (ti, tj) = n hops × E rbit + ( n hops-1) × E Lbit (1)\par
Where E bit (ti, tj)\par
= the average energy consumption for sending one bit of data from t i to tile t j , n hops = the number of routers the bit traverses from tile t i to tile t j , E rbit = the energy consumed by the router for transporting one bit of data, E Lbit = the energy consumed by unit link/channel for transporting one bit of data. For the NoC networks with unequal link length, the ((nhops -1) x E Lbit ) can be replaced as the summation of bit energy consumed by each link in the path/route, the bit follows from source tile to the destination tile \hyperref[b23]{[21]}.\par
Hop count is the number of routers the bit traverses from source tile to tile destination tile. The communication energy model \hyperref[b7]{[7]} for the network on chip clearly shows that the latency and power consumption linearly relates to the average number of hops the packet traverse, hence to the network topology. So we will optimize the latency and power consumption by reducing the hop count between the source tile and destination tile for a given routing function. 
\section[{b) Routing Function in NoC}]{b) Routing Function in NoC}\par
Routing function determines how the data is transmitted from source tile to destination tile. Routing algorithm can be grouped according to different criteria. According to the place where routing decision is made, routing algorithm can be classified as centralized, source and distributed routing algorithm. In centralized the route is chosen by a central controller, in source the route is chosen by a source router prior to a sending the packet, in distributed the route is chosen by an intermediary routers \hyperref[b18]{[16,}\hyperref[b19]{17]}. According to how a route is defined to route the packets, routing algorithm can be deterministic or adaptive. In deterministic routing, one path is calculated between source and destination and routing is done through that fixed path only.\par
Deterministic routing algorithm always routes the packets from source to destination along that same path \hyperref[b17]{[15]}. Deterministic algorithm does not take into account network traffic situation or the network condition before choosing a path from source to destination. In adaptive routing algorithms multiple paths are calculated between source and destination but routing is done in one selected path depending upon the network traffic. In adaptive algorithm network traffic situation (such as network load, traffic condition) are taken into consideration. Limitations of adaptive routing algorithm are its implementation cost, complexity and more power consumption \hyperref[b18]{[16]}. Deterministic routing algorithm is popular in NoC due to simplicity, low latency, simple routing logic, packet reach destination in correct order and reordering is not necessary \hyperref[b7]{[7]}. It is a greedy algorithm because it always chooses a shortest path to deliver a packet from source to destination \hyperref[b19]{[17]}.\par
The design space of efficient deadlock-free routing is an important aspect which is more implicitly affected by the routing algorithm which determines which routes packets can take from source to destination. A deadlock is a situation where packets are involved in a circular wait for resources. Deadlock freedom is an important property for networks, since a packet deadlock can destroy possibilities of communication \hyperref[b20]{[18]}. Deadlocks in a network may block communication between cores and may even lead to a complete failure of network. Therefore it is essential to have algorithms which have ability to handle them. The deterministic routing \hyperref[b7]{[7]} (e.g. XY routing \hyperref[b16]{[14,}\hyperref[b21]{19]} and odd-even routing \hyperref[b17]{[15,}\hyperref[b21]{19]}) are the most widely used deadlock free routing algorithms for the popular 2Dmesh based on chip networks. 
\section[{III.}]{III.} 
\section[{Proposed Methodology}]{Proposed Methodology}\par
In the presented work, an energy conscious topology augmentation methodology is proposed for application specific on-chip interconnection networks. In the proposed methodology a customized NoC topology is synthesized by tailoring the regular 2D mesh topology to achieve energy efficient communication.   {\ref 1}clearly shows that dynamic communication energy linearly relates to the number of routers/hops the packet traverses from the source tile to the destination tile i.e. as the routers in communication path increases, the communication energy also increases. In the regular grid like NoC architecture, there is lack of fast path between two distant nodes so the packets have to traverse many hops between any two remotely situated nodes (source and destination), leading to poor dynamic communication energy dissipation. If we can able to reduce the number of hops in the communication path for a chosen routing function, the considerable amount of energy saving can be achieved in the regular NoC architecture. The reduction in the number of hops in communication path can be done by augmenting the regular mesh by inducing significant shortcut links according to the application characteristics and also constraining parameters such as length of the shortcut link and the port availability per tile. The length of the shortcut link is constrained because in NoC communication generally needs to be clock synchronized and to avoid the long wiring complexity and area overhead short links are generally preferred. The port availability per tile means add the shortcut link to a tile only if there free port is available. The augmentation of regular topology can be done by adding the significant shortcut links to the communication path segments which are carrying maximum traffic load for all the communication/routing paths for a routing function while taking the above mentioned constraints into consideration. In the proposed methodology these significant shortcut links are find out with the help of modified KMP string matching algorithm \hyperref[b14]{[12]}.\par
Figure \hyperref[fig_0]{1} gives architecture of the proposed methodology. The proposed methodology augments the regular 2D mesh topology which is customized using any of the deterministic routing function. In the proposed methodology the routing paths (decided according to chosen deterministic routing function) are input to the modified KMP \hyperref[b14]{[12]} string matching algorithm. Here this algorithm actually dealing with the routing paths as a string. This algorithm find out the path segments of 3 consecutive and 2 consecutive links (in other words of 4 hops and 3 hops respectively) which are common in other routing paths and also gathers non common path segments. In the next step the proposed methodology arranges all these segments (common sub paths of 4 \& 3 hops and non-common segments) in the descending order of total communication energy consumed by these segments. This ordering has been done so that the segments with higher dynamic communication energy consumption will be considered earlier or in other words the segments which carry the maximum traffic load can be addressed earlier, so that maximum benefits can be achieved. After that, it will add the shortcut link to the routing paths which contains that segment in the regular 2D mesh topology according to the order by keeping in check the input constraints (port availability per tile). Here adding the shortcut link to segment of 3 consecutive links or to segment of 2 consecutive links means skipping 2 hops or 1 hop in the corresponding routing path respectively. Hence by doing this we are constraining the length of additional link (shortcut link) in the augmented topology. This augmented topology is referred as shortcut inclusive 2D mesh (SI-2D mesh). For the analysis of various performance parameters SI-2D mesh is validated on NoC simulator NC-G-SIM \hyperref[b22]{[20]}. 
\section[{IV.}]{IV.} 
\section[{Experimental Results}]{Experimental Results}\par
The performance of SI-2D mesh derived from the regular 2D mesh is validated on a network on chip simulator NC-G-SIM. It is a discrete event cycle accurate simulator for Network-on-Chip performance simulation \hyperref[b22]{[20]}. NC-G-SIM supports regular as well as irregular topology framework with source and table  {\ref based} routing. E Lbit is calculated according to the analytical energy model presented in \hyperref[b24]{[8]} \hyperref[b9]{[9]}; E rbit for a router is calculated the help of power simulator Orion \hyperref[b10]{[10]} for 0.18?m t echnology. The c ommunication is as sumed t o be of constant bit rate. Number of application (traffic) characteristics data sets were randomly generated using TGFF \hyperref[b12]{[11]}, with diverse bandwidth requirement of the IP Cores and randomly generated communication bandwidth requirement. The simulation is run for 10000 clock cycles. The average total communication energy per flit received at destination and average per flit latency are taken as performance metric. The methodology is applied to 6 set of different 2D mesh topology, for each topology 10 different test cases were generated and executed. After having experimented on number of topology sets, the average of obtained results is represented to demonstrate the effectiveness of the proposed methodology. The configuration files for a given traffic pattern are generated using the proposed methodology and supplied to the simulator as an input. As shown in Figure \hyperref[fig_1]{2}, the short cut inclusive 2D mesh (SI-2D mesh) generated using the proposed methodology saves about on average 32.79\% of dynamic communication energy consumption compared to regular 2D mesh because SI-2D mesh needs less number of hops to traverse from the source tile to the destination tile, leading to reduced dynamic communication energy and latency. Figure \hyperref[fig_2]{3} shows comparison in terms of average per flit latency between 2D mesh and SI-2D mesh for various topologies and it depicts that the average latency per flit gets reduced by on average of 16.22\% in SI-2D mesh compared to the regular 2D mesh . It is clear that we are getting marginal reduction in latency as compared to the dynamic communication energy; the reason behind this is the occurrence of the congestion due to the generation of hotspot at the induced routers which are heavily loaded as they are bearing the traffic load which was earlier getting spread over multiple routers. However still there is gain in latency as the switching delay in path from source to destination for various application characteristics is reduced due to decrease in number of routers in the corresponding paths.\par
V. 
\section[{Conclusion}]{Conclusion}\par
In this paper, a greedy energy conscious topology augmentation methodology for on-chip interconnection networks is proposed. Using the proposed methodology a shortcut inclusive topology is designed according to the traffic characteristics. The proposed methodology is greedy but fast and uses fast modified KMP string matching algorithm \hyperref[b14]{[12]} for exploring the effective and efficient shortcuts to be augmented in the given regular architecture. The experimental result clearly shows that shortcut inclusive topology generated using proposed methodology is able to reduce dynamic communication energy leading to significant energy savings and also reduction in the average per flit latency as compared to the regular topology.\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Figure 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Figure 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Figure 3 :}\end{figure}
 		 		\backmatter  			  				\begin{bibitemlist}{1}
\bibitem[Dick et al. ()]{b12}\label{b12} 	 		\textit{},  		 			R P Dick 		,  		 			D L Rhodes 		,  		 			W Wolf 		.  		1998.  	 
\bibitem[Ogras Umit and Marculescu ()]{b4}\label{b4} 	 		\textit{},  		 			Y Ogras Umit 		,  		 			R Marculescu 		.  		2005.  	 
\bibitem[Kahng et al. ()]{b10}\label{b10} 	 		\textit{},  		 			A B Kahng 		,  		 			B Li 		,  		 			L S Peh 		,  		 			K Samadi 		.  		2009.  	 
\bibitem[Adamu et al. ()]{b19}\label{b19} 	 		 			G Adamu 		,  		 			P Chejara 		,  		 			A Garko 		,  		 			B 		.  		\textit{Review of deterministic routing algorithm for network-onchip. International conference on science, technology and management},  				2015.  	 
\bibitem[and South Pacific Design Automation Conference]{b8}\label{b8} 	 		\textit{and South Pacific Design Automation Conference},  				p. .  	 
\bibitem[Application Specific Network-on-Chip Architecture Customization via Long Range Link Insertion]{b5}\label{b5} 	 		\textit{Application Specific Network-on-Chip Architecture Customization via Long Range Link Insertion},  		 	 
\bibitem[Holsmark et al. ()]{b20}\label{b20} 	 		‘Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions’.  		 			R Holsmark 		,  		 			M Palesi 		,  		 			S Kumar 		.  	 	 		\textit{Digital System Design: Architectures, Methods and Tools, 9th EUROMICRO Conference},  				 (Dubrovnik)  		2006. p. .  	 
\bibitem[Hu and Marculescu ()]{b7}\label{b7} 	 		‘Energy and performance-aware mapping for regular NoC architectures’.  		 			J Hu 		,  		 			R Marculescu 		.  	 	 		\textit{Computer-Aided Design of Integrated Circuits and Systems}  		2005. 24 p. .  	 
\bibitem[George ()]{b15}\label{b15} 	 		‘Energy consumption in networks on chip: efficiency and scaling’.  		 			B George 		.  	 	 		\textit{IEEE 15 th International Symposium},  				2009. p. .  	 
\bibitem[Wadhwani et al. ()]{b23}\label{b23} 	 		‘Energy Efficient Mapping in 3D Mesh Communication Architecture for NoC’.  		 			P Wadhwani 		,  		 			N Chaudhary 		,  		 			D Singh 		.  	 	 		\textit{Global Journal of Computer Science, and Technology (GJCST-E) on Network, Web \& Security}  		2013. 13 p. .  	 
\bibitem[Umamaheswari and Rajapaul ()]{b1}\label{b1} 	 		‘Energy, Throughput and Area Evaluation of Regular and Irregular Network on Chip Architectures’.  		 			S Umamaheswari 		,  		 			P Rajapaul 		,  		 			J 		.  	 	 		\textit{Journal of Distributed and Parallel Systems}  		2011. 2  (5) .  	 	 (IJDPS) 
\bibitem[Hu and Marculescu ()]{b24}\label{b24} 	 		‘Energy-aware mapping for tile-based NoC architectures under performance constraints’.  		 			J Hu 		,  		 			R Marculescu 		.  	 	 		\textit{Proceedings of the Asia},  				 (the Asia)  		2003.  	 
\bibitem[Dehyadgari et al. ()]{b16}\label{b16} 	 		\textit{Evaluation of Pseudo Adaptive XY Routing Using an Object Oriented Model for NOC},  		 			M Dehyadgari 		,  		 			M Nickray 		,  		 			A Kusha 		,  		 			Z Navabi 		.  		2005.  	 
\bibitem[Bei and Sheqin ()]{b2}\label{b2} 	 		‘Floorplanning and Topology Generation for Application-Specific Network-on-Chip’.  		 			Yu Bei 		,  		 			Dong Sheqin 		.  	 	 		\textit{Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific},  				2010. IEEE. p. .  	 
\bibitem[Choudhary et al. ()]{b9}\label{b9} 	 		‘GA based congestion aware topology generation for application specific NoC’.  		 			N Choudhary 		,  		 			M S Gaur 		,  		 			V Laxmi 		,  		 			V Singh 		.  	 	 		\textit{Sixth IEEE International Symposium Electronic Design, Test and Application (DELTA)},  				2011. p. .  	 
\bibitem[Duato et al. ()]{b17}\label{b17} 	 		\textit{Interconnection Networks: An Engineering Approach},  		 			J Duato 		,  		 			S Yalamanchili 		,  		 			L Ni 		.  		2003. San Francisco: Morgan Kaufmann Publishers.  	 
\bibitem[Thomas et al. ()]{b14}\label{b14} 	 		\textit{Introduction to Algorithms},  		 			H Thomas 		,  		 			Charles E Cormen 		,  		 			Ronald L Leiserson 		,  		 			Clifford Rivest 		,  		 			Stein 		.  		2009. Cambridge, Massachusetts London, England: The MIT Press.  	 	 (3 rd edition) 
\bibitem[Ogras Umit and Marculescu ()]{b6}\label{b6} 	 		‘It's a Small World After All: NoC Performance Optimization via Long Range Link Insertion’.  		 			Y Ogras Umit 		,  		 			R Marculescu 		.  	 	 		\textit{IEEE}  		2006. 14  (7) .  	 
\bibitem[Vyas et al. ()]{b22}\label{b22} 	 		‘NC-G-SIM: A Parameterized Generic Simulator for 2D-Mesh, 3D Mesh \& Irregular On-chip Networks with Table-based Routing’.  		 			K Vyas 		,  		 			N Choudhary 		,  		 			D Singh 		.  	 	 		\textit{Global Journal of Computer Science and Technology (GJCST-E) on Network, Web \& Security}  		2013. 13 p. .  	 
\bibitem[Choudhary ()]{b21}\label{b21} 	 		‘Network-on-Chip: A New SoC Communication Infrastructure Paradigm’.  		 			N Choudhary 		.  	 	 		\textit{International Journal of Soft Computing and Engineering (IJSCE)}  		 2231-2307.  		2012. 1 p. .  	 
\bibitem[Orion 2.0: A fast and accurate NoC power and area model for early-stage design space exploration Proceedings of the conference on Design, Automation and Test in Europe]{b11}\label{b11} 	 		‘Orion 2.0: A fast and accurate NoC power and area model for early-stage design space exploration’.  	 	 		\textit{Proceedings of the conference on Design, Automation and Test in Europe},  				 (the conference on Design, Automation and Test in Europe)  		p. .  	 
\bibitem[Singh]{b18}\label{b18} 	 		\textit{Performance evaluation of different routing algorithm in network on chip master dissertation National Institute of Technology Rourkella},  		 			J K Singh 		.  		Odesha.  	 
\bibitem[Fuks and Lawniczak ()]{b3}\label{b3} 	 		‘Performance of data networks with random links’.  		 			H Fuks 		,  		 			A Lawniczak 		.  	 	 		\textit{Mathematics and Computers in Simulation}  		1999. 51.  	 
\bibitem[Dally and Towles ()]{b0}\label{b0} 	 		‘Route packets, Not wires: On-chip interconnection networks’.  		 			W J Dally 		,  		 			B Towles 		.  	 	 		\textit{Design Automation Conference, Proceedings},  				2001. IEEE. p. .  	 
\bibitem[TGFF: task graphs for free IEEE Computer Society, Proceedings of the 6th international workshop on Hardware/software co-design]{b13}\label{b13} 	 		‘TGFF: task graphs for free’.  	 	 		\textit{IEEE Computer Society, Proceedings of the 6th international workshop on Hardware/software co-design},  				p. .  	 
\end{bibitemlist}
 			 		 	 
\end{document}
