Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology

Authors

  • Md. Masood Ahmad

  • Dr. K. Manjunathachari

  • Dr. K.Lalkishore

Keywords:

peak leakage, average leakage, peak power, average power, 13transistors full adder, run-time leakage

Abstract

In this paper a new full adder is proposed The number of Transistors used in the proposed full adder is 13 Average leakage is 62 of conventional 28 transistor CMOS full adder The leakage power reduction results in overall power reduction The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tools

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How to Cite

Md. Masood Ahmad, Dr. K. Manjunathachari, & Dr. K.Lalkishore. (2016). Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology. Global Journal of Computer Science and Technology, 16, 25–31. Retrieved from https://computerresearch.org/index.php/computer/article/view/1478

 
Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology

Published

2016-01-15

Issue

Vol. 16 No. (2016): GJCST-A Hardware

Section

Articles

License

Copyright (c) 2016 Authors and Global Journals Private Limited

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.