@incollection{,
	
					
					
					0167FC5EA48CA8BF2F000AF2E323B8C6
				,
	author={{Md. MasoodAhmad} and {Dr. K.Manjunathachari} and {Dr.K.Lalkishore} and {GITAM UNIVERSITY}},
	journal={{Global Journal of Computer Science and Technology}},
	journal={{GJCST}}0975-41720975-435010.34257/gjcst,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}1612531
}

@incollection{b0,
	
	
		,
	title={{A comparative performance analysis of various CMOS design techniques for XOR and XNOR circuits}}
		,
	author={{
			AdarshShiv Shankar Mishra
		} and {
			RKKumar Agrawal
		} and {
			Nagaria
		}}
		
		
	
	
		,
	journal={{International Journal on Emerging Technologies}}
		0975-8364
		
	

}

@incollection{b1,
	
	
		,
	title={{Power and Delay Comparison in between Different types of Full Adder Circuits}}
		,
	author={{
			ASaradindu Panda
		} and {
			BBanerjee
		} and {
			DrA KMaji
		} and {
			Mukhopa
		}}
		
		
		
	
	
		,
	journal={{International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering}}
		2278 -8875
		
	

}

@incollection{b2,
	
	
		,
	title={{True Energy-Perfor-mance Analysis of the MTJ-Based Logic-in-Memory Architecture}}
		,
	author={{
			DejanFengbo Ren
		} and {
			Markovi
		}}
		
	
	
		,
	journal={{IEEE TRANSACTIONS ON ELECTRON DEVICES}}
		
			57
			5
			,
	year={MAY 2010}
		
	

}

@incollection{b3,
	
	
		,
	title={{On the Design of High-Performance CMOS 1-Bit Full Adder Circuits}}
		,
	author={{
			VShivshankar Mishra
		} and {
			DrR ANarendar
		} and {
			Mishra
		}}
		
		
	
	
		,
	booktitle={{International Conference on VLSI, Communication and Instrumentation}}
				
			,
	year={2011}
		
	

}

@incollection{b4,
	
	
		,
	title={{Highly Reliable and Low-Power Full Adder Cell}}
	
	
		,
	booktitle={{IEEE International Conference on Nanotechnology}}
				
			,
	year={August 15-18, 2011}
		
	
	,
	note={Walid Ibrahim1, Azam Beg1 and Valeriu Beiu}

}

@incollection{b5,
	
	
		,
	title={{New Design Methodologies for high speed mixed mode CMOS Full adder circuits}}
		,
	author={{
			SubodhWairya
		} and {
			RajendraKumar Nagaria
		} and {
			SudarshanTiwari
		}}
		
		
	
	
		,
	journal={{International Journal of VLSI design and Communication Systems}}
		
			2
			2
			,
	year={June 2011}
		
	

}

@incollection{b6,
	
	
		,
	title={{Comparative Performance Analy sis of XOR-XNOR Function Based High-Speed CM OS Full Adder Circuits For Low Voltage VLSI Design}}
		,
	author={{
			SubodhWairya
		} and {
			RajendraKumar Nagaria
		} and {
			SudarshanTiwari
		}}
		
		
	
	
		,
	journal={{International Journal of VLSI design and Communication Systems}}
		
			3
			2
			,
	year={April 2012}
		
	

}

@incollection{b7,
	
	
		,
	title={{Design of Robust, Energy-Efficient Full Adders for Deep Submicrometer Design Usi ng Hybrid-CMOS Logic Style}}
		,
	author={{
			AshokSumeer Goe
		} and {
			SeniorKumar
		} and {
			MagdyAMember
		} and {
			Bayoumi
		}}
		
		
		
	
	
		,
	booktitle={{IEEE TRANSACTIO-NS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}}
				
			,
	year={Dec 2006}
			14
		
	

}

@book{b8,
	
	
		,
	title={{Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design}}
		,
	author={{
			RajendraSubodhwairya
		} and {
			SudarshanKumar
		} and {
			Tiwari
		}}
		
		
		ID 173079
		
			,
	publisher={Hindawi Publishing Corporation VLSI Design}
			2012
		
	

}

@incollection{b9,
	
	
		,
	title={{A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design}}
		,
	author={{
			AnuTonk
		} and {
			ShilpaGoyal
		}}
		
	
	
		,
	journal={{International Journal on Recent and Innovation Trends in Computing and Communication}}
		2321-8169
		
	

}

@incollection{b10,
	
	
		,
	title={{A Novel High-Performance CMOS 1-Bit Full-Adder Cell}}
		,
	author={{
			AhmedMShams
		} and {
			MagdyABayoumi
		}}
		
	
	
		,
	journal={{IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS}}
		
			47
			5
			,
	year={MAY 2000}
		
	

}

@incollection{b11,
	
	
		,
	title={{Analysis of Low Power 1-bit Adder Cells using different xor-xnor gates}}
		,
	author={{
			SampathDeepa
		} and {
			Kumar
		}}
		
	
	
		,
	booktitle={{IEEE International Conference on Computational Intelligence and Communication Technology}}
				
			,
	year={2015}
		
	

}

@book{b12,
	
	
		,
	title={{High-Speed VLSI Arithme tic Units: Adders and Multipliers}}
		,
	author={{
			Prof
		} and {
			GVojin
		} and {
			Oklobdzija
		}}
		
		
		
	

}

@incollection{b13,
	
	
		,
	title={{Comparative Study of Different Types of Full Adder Circuits}}
		,
	author={{
			Sansar Chand Sankhyan
		}}
	
	
		,
	journal={{Sansar Chand Sankhyan Int. Journal of Engineering Research and Applications}}
		2248-9622
		
			3
			,
	year={Sep-Oct 2013}
		
	

}

@incollection{b14,
	
	
		,
	title={{Analysis of various full adder circuit on various parameters for low power}}
		,
	author={{
			Mr
		} and {
			MrShashankMangla
		} and {
			Saxena
		}}
		
		
	
	
		,
	journal={{International Journal of Engineering and Technical Research}}
		2321-0869
		
			5
			,
	year={May 2015}
		
	

}

@incollection{b15,
	
	
		,
	title={{Analysis and Comparison on Full Adder Block in Submicron Technology}}
		,
	author={{
			MassimoAlioto
		} and {
			GaetanoPalumbo
		}}
		
	
	
		,
	booktitle={{IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}}
				
			,
	year={Dec 2002}
			10
		
	

}

@incollection{b16,
	
	
		,
	title={{Robust Subthreshold Full Adder Design Technique}}
		,
	author={{
			AminulIslam
		} and {
			AleImran
		} and {
			Mohd
		} and {
			Hasan
		}}
		
		
		
	
	
		,
	booktitle={{Internatio-nal Conference on Multimedia, Signal Processing and Communication Technologies}}
				
			,
	year={2011}
		
	

}

@incollection{b17,
	
	
		,
	title={{A Study of Full Adder Circuits: from Power and Speed of Operation}}
		,
	author={{
			ManojDuhan
		} and {
			KusumDala
		} and {
			ViploveKumar
		}}
		
		
	
	
		,
	journal={{An International Journal of Engineering Sciences}}
		
			10
			,
	year={June 2014}
		
	

}

@book{b18,
	
	
		,
	author={{
			AnandRaghunathan
		} and {
			NecUsa
		} and {
			NirajKJha
		}}
		
		
		,
	title={{HIGH-LEVEL POWER ANALYSIS AND OPTIMIZATION}}
				
		
			Princeton University, Sujit Dey NECUSA
		
	

}

@book{b19,
	
	
		,
	title={{}}
		,
	author={{
			PAnantha
		} and {
			Chandrakasan
		} and {
			WMit; Robert
		}}
		
		
		
	

}

@book{b20,
	
	
		,
	author={{
			UniversityBrodersen
		} and {
			/Of California
		} and {
			Berkeley
		}}
		
		
		,
	title={{LOW POWER DIGITAL CMOS DESIGN}}
				
	

}

@book{b21,
	
	
		,
	author={{
			GaryYeap
		}}
		,
	title={{PRACTICAL LOW POWER DIGITAL VLSI DESIGN}}
				
	

}

@book{b22,
	
	
		,
	title={{University Califomia and Massoud Pedram, University of Southem Califomia}}
		,
	author={{
			JanMRabaey
		} and {
			;Low Power Design
		} and {
			Methodologies
		}}
		
		
		
	

}

@book{b23,
	
	
		,
	author={{
			MohamedMohabanis
		} and {
			Elmasry
		}}
		
		,
	title={{Multi-Threshold CMOS Digital Circuits Managing Leakage Power}}
				
	

}

@book{b24,
	
	
		,
	author={{
			HENeil
		} and {
			DavidMoneyWeste
		} and {
			Harris
		}}
		
		
		,
	title={{CMOS VLSI Design: A Circuits and Systems Perspective}}
				
	

}

@book{b25,
	
	
		,
	author={{
			NikhilJayakumar
		} and {
			SuganthPaul
		} and {
			RajeshGarg
		} and {
			KanupriyaGulati
		} and {
			PSunil
		} and {
			Khatri
		}}
		
		
		
		
		
		,
	title={{Minimizing and Exploiting Leakage in VLSI Design}}
				
	

}

@book{b26,
	
	
		,
	author={{
			PRVander Meer
		} and {
			AVan Staveren
		} and {
			AH MVan Roermund
		}}
		
		
		,
	title={{LOWPOWER DEEP SUB-MICRON CMOS LOGIC: Sub-threshold Current Reduction}}
				
	

}

@incollection{b27,
	
	
		,
	title={{Leakage Power Reduction in CMOS VLSI Circuits}}
		,
	author={{
			PushpaSaini
		} and {
			RajeshMehra
		}}
		
	
	
		,
	journal={{International Journal of Computer Applications}}
		
			55
			09758887
			,
	year={October 2012}
		
	

}

@incollection{b28,
	
	
		,
	title={{Digital Integrated Circuits: Design approach}}
		,
	author={{
			JanMRabaey
		} and {
			AnanthaChadrakasan
		} and {
			BorivojeNikolic
		}}
		
		
	
	
		,
	booktitle={{of IEEE International Conference on Power, Control and Embedded System (ICPCES)}}
				
			,
	year={28 Nov.-1Dec. 2010}
		
	

}

@book{b29,
	
	
		,
	title={{Minimum Dynamic power CMOS design with variable input delay logic}}
		,
	author={{
			TejaswiRaja
		}}
		
			,
	year={May 2004}
		
	

}

@book{b30,
	
	
		,
	author={{
			PSaraju
		} and {
			NagarajanMohanty
		} and {
			EliasRanganathan
		} and {
			PriyadarsanKougianos
		} and {
			Patra
		}}
		
		
		
		
		,
	title={{Low-Power High-Level Synthesis for Nanoscale CMOS Circuits}}
				
	

}

@incollection{b31,
	
	
		,
	title={{A 10-transistor lowpower high-speed full adder cell}}
		,
	author={{
			Mahmoud
		} and {
			MBayoumi
		}}
		
	
	
		,
	booktitle={{Proc. ISCAS99}}
				ISCAS99Orlando, FL
		
			,
	year={June 1999}
			4346
		
	

}

@book{b32,
	
	
		,
	title={{Low-Power CMOS VLSI Circuit Design}}
		,
	author={{
			KRoy
		} and {
			SPrasad
		}}
		
		
			,
	year={2000}
			,
	publisher={Wiley Intersci}
			,
	address={New York}
		
	

}

@book{b33,
	
	
		,
	title={{Low-Power Digital VLSI Design: Circuits and Systems}}
		,
	author={{
			ABellaouar
		} and {
			MElmasry
		}}
		
		
			,
	year={1995}
			,
	publisher={Kluwer Academic}
			,
	address={Boston, MA}
		
	

}

@book{b34,
	
	
		,
	title={{Low Power Digital CMOS Design}}
		,
	author={{
			RChandrakasan
		} and {
			Brodersen
		}}
		
		
			,
	year={1995}
			,
	publisher={Kluwer Academic}
			,
	address={Boston, MA}
		
	

}

@incollection{b35,
	
	
		,
	title={{Low-power logic styles: CMOS versus pass-transistor logic}}
		,
	author={{
			RZimmermann
		} and {
			WFichtner
		} and {
			; MBayoumi
		}}
		
		
	
	
		,
	journal={{IEEE Trans. Circuits Syst.Part II}}
		
			32
			478481
			,
	year={July 1997. May 2000}
		
	
	,
	note={IEEE J. Solid-State Circuits}

}

@incollection{b36,
	
	
		,
	title={{Newefficient designs for XOR and XNOR function on the transistor level}}
		,
	author={{
			JWang
		} and {
			SFang
		} and {
			Feng
		}}
		
		
	
	
		,
	journal={{IEEE J. Solid-State Circuits}}
		
			29
			780786
			,
	year={July 1994}
		
	

}

@incollection{b37,
	
	
		,
	title={{Design and Analysis of 10-transistor Full Adders using Novel XOR-XNOR Gates}}
		,
	author={{
			HTBui
		} and {
			AKAl-Sheraidah
		} and {
			YWang
		}}
		
		
	
	
		,
	journal={{Proceedings of ICSP}}
		
			,
	year={2000}
		
	

}

@incollection{b38,
	
	
		,
	title={{Gate-Diffusion Input(GDI): A Power-Efficient Method for Digital Combinational Circuits}}
		,
	author={{
			AMorgenshtein
		} and {
			AFish
		} and {
			AWagner
		}}
		
		
	
	
		,
	journal={{IEEE Trans. VLSI Syst}}
		
			
			,
	year={Oct. 2002}
		
	

}

@incollection{b39,
	
	
		,
	title={{A novel high performance CMOS 1-bit full adder cell}}
		,
	author={{
			AMShams
		} and {
			MABayoumi
		}}
		
	
	
		,
	journal={{IEEE Trans. Circuits and Systems-II}}
		
			47
			5
			
			,
	year={2000}
			,
	publisher={Analog digital Signal Process}
		
	

}

@incollection{b40,
	
	
		,
	title={{Design and Analysis of 10-Transistor Full Adders Using XOR-XNOR Gates}}
		,
	author={{
			HTBui
		} and {
			YWang
		} and {
			YJiang
		}}
		
		
	
	
		,
	journal={{IEEE Trans. Circuits and Syst}}
		
			II
			1
			
			,
	year={Jan. 2002}
		
	
	,
	note={Analog Digit. Signal Process.}

}

@book{b41,
	
	
		,
	title={{) CMOS Based 1-Bit Full Adder Cell for Low-Power Delay Product}}
		,
	author={{
			DGarg
		} and {
			MKRai
		} and {
			/Ijecct
		}}
		
		
		
			,
	year={2012}
			2
		
	

}

@incollection{b42,
	
	
		,
	title={{A review of 0.18um full adder performances for tree structure arithmetic circuits}}
		,
	author={{
			CHChang
		} and {
			JGu
		} and {
			MZhang
		}}
		
		
	
	
		,
	booktitle={{IEEE Trans:Very Large scale Integration (VLSI) System}}
				
			,
	year={2005}
			13
			
		
	

}

@incollection{b43,
	
	
		,
	title={{Mixed Full Adder topologies for high-performance low-power arithmetic circuits}}
		,
	author={{
			MAlioto
		} and {
			GDiCataldo
		} and {
			GPlumbo
		}}
		
		
	
	
		,
	journal={{Microelectronics Journal}}
		
			38
			
			,
	year={2007}
		
	

}

@book{b44,
	
	
		,
	title={{Proposing a Novel Low-Power High-Speed Mixed GDI Full Adder Topology}}
		,
	author={{
			AdarshKumar Agrawal
		} and {
			ShivshankarMishra
		} and {
			RKNagaria
		}}
		
		
		
	
	,
	note={accepted in Proceeding}

}