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\title{Design and Analysis of Low Run-Time Leakage in a 13 Transistors Full Adder in 45nm Technology}
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\begin{document}

             \author[1]{Md. Masood  Ahmad}

             \author[2]{Dr. K.  Manjunathachari}

             \author[3]{Dr.  K.Lalkishore}

             \affil[1]{  GITAM UNIVERSITY}

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\date{\small \em Received: 11 December 2015 Accepted: 4 January 2016 Published: 15 January 2016}

\maketitle


\begin{abstract}
        


In this paper a new full adder is proposed. The number of Transistors used in the proposed full adder is 13.Average leakage is 62% of conventional 28 transistor CMOS full adder. The leakage power reduction results in overall power reduction. The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tools.

\end{abstract}


\keywords{peak leakage, average leakage, peak power, average power, 13transistors full adder, run-time leakage.}

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\let\tabcellsep& 	 	 		 
\section[{I. Introduction}]{I. Introduction}\par
n this paper various 1-bit full adders are considered for leakage analysis. A 13 Transistor Full adder is designed and analysed for low leakage. Full adders considered for analysis in this paper are Complimentary MOS implementation of full adder \hyperref[b28]{[29]}, Mirror full adder \hyperref[b28]{[29]}, Transmission gate full adder \hyperref[b28]{[29]}, Manchester full adder \hyperref[b28]{[29]}, Complimentary pass transistor logic full adder, Low power Full adder, Lean integration with pass transistor full adder, \hyperref[b18]{20} Transistor Transmission gate full adder, Improved 14 transistor Full adder, SERF Full adder, GDI XOR full adder, 10 transistor full adder, 9A full adder, 9B full adder, 13A full adder, 8 transistor full adder and proposed 13 transistor full adder. full adders and their implementation style at transistor level includeng the proposed full adder is as follows. CMOS 28 Transsistor Full Adder: Conventional CMOS Full Adder consists of 28 transistors as shown in fig. 1.From the following equations one can design CMOS 28 Transistor full adder circuit \hyperref[b28]{[29]}.CO = AB + [A + B]C in (1) S = ABCi + CO(A + B + Ci ) (2)\par
Mirror Adder: The fig.  {\ref 2}. shows Mirror Adder. An improved adder circuit, also called as "Mirror Adder" \hyperref[b1]{[2]}. This is a clever implementation of the propagate/generate/delete function when either D or G is high, CO is set VDD of Gnd, respectively. When the conditions for propagate are valid (or P is 1), the incoming carry is propagated to CO.\par
Figure  {\ref 2}: Mirror Adder \hyperref[b28]{[29]} Complimentary pass transistor logic: The CPL Full Adder has 18 transistors \hyperref[b32]{[33]} and is based on NMOS passtransistor logic as shown in fig.  {\ref 5}          Figure 12: Gate diffusion XOR Full Adder \hyperref[b38]{[39]} Figure 13: Gate diffusion XNOR Full Adder \hyperref[b38]{[39]} Figure 14: 10T Full Adder \hyperref[b40]{[41]} Figure 15: 9A Full Adder \hyperref[b37]{[38]} XNOR because there is no direct connection with ground.9B Full adder \hyperref[b37]{[38]} is as shown in fig. 16.\par
13A Full Adder: The other type of 10 transistors 1-bit full adder is 13A full adder, which have better critical delay than the 10 transistors SERF full adder in all loading conditions. 13A adder \hyperref[b10]{[11]}comes out as best when compared with respect to low power and delay. 13A adder is built using SERF XNOR and INV XNOR. The SER Full Adder: SERF adder \hyperref[b10]{[11]} reuses charge by the energy recovering logic and hence consumes less power than non-energy recovering logic. SERF adder has no direct path to the ground, therefore power dissipation is reduced. The charge stored at the load capacitance is reapplied to the control gates. The joint effect of these two things makes the SERF adder an energy efficient design.SERF Full adder as as shown in fig. 11.\par
GDI XOR Full Adder: GDI \hyperref[b38]{[39]}technique is implemented to design a high performance and low power full adder.GDI cell contains three inputs-G (common state input of NMOS and PMOS), N (input to the source or drain of NMOS) and P (input to the source or drain of PMOS). GDI XOR Full adder as shown in fig. 12.\par
10 Transistor Full Adder: Full adder using 10T uses more than one logic style for the implementation and it is called as Hybrid logic design style. The number of transistors count is 10. 10 Transistor Full adder \hyperref[b40]{[41]}is as shown in fig. 14. 
\section[{II. Simulation Results}]{II. Simulation Results}\par
Simulation results are presented in table I for the analysis. The table I shows the comparision of average leakage power, peak leakage power, average power and peak power in 28 Transistor full adder, Mirror, TG, Manchester, CPL, LEAP, 20T, 14T, SERF, GDI XOR, GDi XNOR, 10T, 9A,9B, 13A, 8T and proposed 13 Transistors full adders.  
\section[{III. Conclusion}]{III. Conclusion}\par
Below 70 nm technologies run-time leakage power dominates the dynamic power.So one should come up with new full adder which consumes less leakage power compared to dynamic power one such attempt is discussed in this paper. 
\section[{IV. Acknowledgment}]{IV. Acknowledgment}\par
My sincere thanks to my guides Dr. K. Manjunathachari and Dr. K. Lalkishore for their valuable support and encouragement.        \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{P{0.12200956937799043\textwidth}P{0.1762360446570973\textwidth}P{0.18437001594896332\textwidth}P{0.18165869218500796\textwidth}P{0.185725677830941\textwidth}}
Full Adders\tabcellsep Average Leakage\tabcellsep Peak Lekage\tabcellsep Average Power\tabcellsep Peak Power\\
28T\tabcellsep 313.2nW\tabcellsep 34.83uW\tabcellsep 351.1nW\tabcellsep 36.26uW\\
Mirror\tabcellsep 288.3nW\tabcellsep 37.48nW\tabcellsep 317.0nW\tabcellsep 28.75uW\\
TG\tabcellsep 8.9uW\tabcellsep 53.80uW\tabcellsep 41.96uW\tabcellsep 69.14uW\\
Manchester\tabcellsep 9.01uW\tabcellsep 76.24uW\tabcellsep 42.32uW\tabcellsep 115.32uW\\
CPL\tabcellsep 27.86uW\tabcellsep 72.52uW\tabcellsep 39.83uW\tabcellsep 63.03uW\\
LP\tabcellsep 9.13uW\tabcellsep 44.14uW\tabcellsep 35.19uW\tabcellsep 54.44uW\\
LEAP\tabcellsep 29.05uW\tabcellsep 73.88uW\tabcellsep 38.42uW\tabcellsep 73.75uW\\
20T\tabcellsep 11.91uW\tabcellsep 44.62uW\tabcellsep 24.05uW\tabcellsep 41.31uW\\
14T\tabcellsep 7.04uW\tabcellsep 18.6uW\tabcellsep 720nW\tabcellsep 51.89uW\\
SERF\tabcellsep 2.03uW\tabcellsep 33.31uW\tabcellsep 14.5uW\tabcellsep 29.55uW\\
GDI XOR\tabcellsep 158nW\tabcellsep 10.90uW\tabcellsep 252nW\tabcellsep 24.56uW\\
GDI XNOR\tabcellsep 151.8nW\tabcellsep 15.53uW\tabcellsep 330.4nW\tabcellsep 16.18uW\\
10T\tabcellsep 7.83uW\tabcellsep 31.97uW\tabcellsep 12.55uW\tabcellsep 31.90uW\\
9A\tabcellsep 12.48uW\tabcellsep 24.96uW\tabcellsep 116.1nW\tabcellsep 29.35uW\\
9B\tabcellsep 85.78nW\tabcellsep 33.95uW\tabcellsep 12.45uW\tabcellsep 27.39uW\\
13A\tabcellsep 8.8uW\tabcellsep 38.14uW\tabcellsep 21.17uW\tabcellsep 43.03uW\\
8T\tabcellsep 15.76uW\tabcellsep 34.95uW\tabcellsep 20.36uW\tabcellsep 31.91uW\\
Proposed 13T\tabcellsep 196.4nW\tabcellsep 17.10uW\tabcellsep 12.67uW\tabcellsep 52.70uW\end{longtable} \par
 
\caption{\label{tab_2}Table 1 :}\end{figure}
 		 		\backmatter  			 \par
Cout is designed using multiplexer.13A Full adder is as shown in fig.  {\ref 17}.\par
8 Transistor Full Adder: It is built using three multiplexers and one inverter \hyperref[b41]{[42]}. The inverter in the circuit speeds up propagation of Cout and also provides complemented Cout signal required for generation of Sum. The xor gate is replaced by xnor gate. So the need for inverter is avoided. This reduces the transistor count to 8. The transistor level implementation of the eight transistor full adder is shown in fig.  {\ref 18}.  Proposed 13 Transistors Full Adder: After having detail analysis we started to work by undertaking different approach so that we can reduce leakage till some extent along with increase in swing and reduce in average power. Then initially we started on investigating on output swing and came to know that by replacing A\textunderscore B it is possible to increase the swing as well as decrease in leakage along with average power. It differs from complementary CMOS in that the source side of the MOS transistor is connected to an input line instead of being connected to power lines. Another important difference is that only one PTL network (either NMOS or PMOS) is sufficient to perform the logic operation. In this circuit sum is calculated from output carry. This proposed full adder resulted low leakage as well as low power as comparing with existed full adder.  			 			  				\begin{bibitemlist}{1}
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\end{document}
