# I. Introduction

any transistor circuits are designed using bipolar junction transistors (BJTs) or MOSFETs. MOSFET designs are usually easier to analyze due to the high gate impedance so this paper focuses on the BJT, and in particular, the common emitter configuration. There will be two types of ac equivalent circuit analyzed in this paper. The first will assume that the emitter bypass capacitor is ideal, i.e. infinite capacitance, and the second will consider a finite capacitor impedance, which significantly increases the complexity of the problem. The coupling capacitors tend to play a lesser role in the ac design parameters so the ideal approximation of these components is reasonably close to the non-ideal case. The output impedance of the source and the input impedance of the load can be factored in after developing the initial model.

The calculations are relatively simple when considering a common emitter amplifier circuit with an resistor values, then often has to modify them to achieve the proper gain (Av), input impedance (Rin), output impedance (Ro), and voltage difference between the collector and emitter (Vce). When working with an ideal bypass capacitor, it is not difficult to determine the proper parameters, but for the finite bypass capacitor the problem is significantly more challenging. This work is mainly intended for engineers, but also professors who may need to evaluate specific amplifier designs and grade the circuits supplied by their students. With regard to professors, if a student submits a design, it is the role of the instructor to evaluate the configuration to determine whether it meets the expected parameters. In other words, the resistor values, and/or the bypass capacitor value needs to be defined. If each student, or team, in a lab is expected to create a different design it will be necessary for the instructor to evaluate each solution to determine whether it meets the given criteria so this work should streamline the procedure.

This paper is organized as follows. First, the design procedure for the dc equivalent common emitter circuit is introduced along with some of its defining equations. Next, the expressions needed to solve for the ac equivalent circuits are developed. This is followed by a brief discussion of the neural network architecture. The next section addresses the finite bypass capacitor and the equations required to analyze the modified circuit. Finally, some conclusions will be discussed and some thoughts for further work.


# II. The Common Emitter Amplifier

The common emitter amplifier circuit is one of the basic configurations introduced when studying the BJT [Sedra and Smith, 2015], [Jaeger, 1997]. It is a voltage amplifier with a reasonably high input impedance and voltage gain. The output impedance can be a bit high as well, but this can be handled by being certain that the input impedance of the follow-up stage is much higher, as for example, an emitter follower circuit. In a transistor circuit there are the dc bias values and the ac signal, but one must look at each of them separately in order to compute the proper operating points.


# M

ideal bypass capacitor, but a much greater amount of effort is needed for the non-ideal case. The former will be considered first. For a given transistor the designer works through a set of calculations to determine the An example circuit is shown in Fig. 1 where the 2N3904 NPN transistor is used with ?=160. The ac input is Vi while the output is taken across the load resistor RL on the right.

Abstract-Transistor amplifier design is an important and fundamental concept in electronics, typically encountered by students at the junior level in electrical engineering. This paper focuses on two configurations that employ neural networks to design bipolar junction transistor circuits. The purpose of this work is to determine which design best fits the required parameters.

Engineers often need to develop transistor circuits using a particular topology, e.g., common emitter, common collector, or common base. These also include a set of parameters including voltage gain, input impedance, and output impedance. For the most part, there are several methodologies that can provide a suitable solution, however the objective of this work is to indicate which external resistors are necessary to yield useful designs by employing neural networks. Here, a neural network has been trained to supply these component values for a particular configuration based on the aforementioned parameters. This should save a significant amount of work when evaluating a particular topology. And it should also permit experimentation with several designs, without having to perform detailed calculations.

Initially, the dc circuit is analyzed with all capacitors considered as open circuits in order to find the currents and voltages from the power supply and biasing resistors. The coupling capacitors isolate the dc component and its circuit equivalent is shown in Fig. 2.


# Figure 2 : The dc equivalent circuit of a common emitter amplifier with ideal capacitors

To determine the dc biasing values the base resistors and source are replaced with their Thevenin equivalent and a single loop circuit is analyzed. For this circuit the Thevenin expressions are as follows where IBis the dc base current:
? ? ? ? ? ? ? ? + = 2 1 2 B B B cc th R R R V V and 2 1 || B B B R R R =(1)
So the loop expression becomes:

( )
0 1 7 . 0 = + + + + ? E B B B th R I I R V ? (2)
After the dc bias values have been determined those sources are set to zero and only the ac components are considered. Recall that the dc voltage sources become short circuits to ground when set to zero. The ac equivalent of the transistor circuit is shown in Fig. 3 using the hybrid -? model. This model is The development of most of the ac equivalent expressions can be found in many texts on microelectronics so they are only summarized here. The total collector current ic is approximated where vbeis the ac base to emitter voltage and VTis the thermal voltage which is usually approximated at 25 mV so that.
? ? ? ? ?? ? ac be T C DC C T be DC C C v V I I V v I i ? ? ? ? ? ? ? ? + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? 1(3)
From now on the ac component is of interest. By superposition the DC sources are shut down, which means that they act like short circuits to ground. By looking at the right hand term from above it can be seen that the ac equivalent is:
be T C c v V I i ? ? ? ? ? ? ? ? =(4)
This is the reciprocal of resistance and is referred to as trans conductance, with symbol gm: where
T C m V I g / = (5) therefore: be m c v g i = (6)
The ac input resistance of the transistor is defined as input voltage divided by input current so the resistance seen at the base is ( )
m be m be b be g v g v i v r ? ? ? = = = (7) Alternatively ( ) ( ) B T T B T C I V V I V I r = = = ? ? ? ? (8)
For the finite bypass capacitor circuit the Tmodel of the BJT will be used so se resistance seen from the emitter to the base will be needed and is written as  


# III. Experimental Procedure

Neural networks are most commonly considered as pattern recognition systems.This author has used them to develop a method of impedance matching using feed-forward neural networks [Hemminger, 2005].They are non-linear systems and are often employed to differentiate between input patterns [Pao, 1989], [Graupe 2013], [Hagan and Demuth].

In order to train the neural networks in this project a set of "for" loops was created in MATLAB? for the four biasing resistors. For all of the tests, the resistor values ranged as shown in table 1. The values of Rin, Ro, Av, and Vce were calculated for all of the resistor combinations. Once this was completed a neural network was trained using the new input values of Rin, Ro, Av, and Vceto compute the four biasing resistor values. In developing the network, the inputs and outputs were normalized to a magnitude of 1 to ensure convergence. For the ideal bypass capacitor circuit there were 5,349 training patterns, limited to realistic values. For example, the gain, Av, was limited to a magnitude of 210, while Vce was held to the range of 2 volts to 12 volts. The test sets consisted of a larger number of patterns, none of which had been used in training.

The neural network package in MATLAB? was utilized to train the networks, employing the Levenberg-Marquardt algorithm, using one hidden layer of 18 sigmoidal (Tanh) neurons each [Demuth and Beale]. Smaller numbers of nodes yielded unacceptable results and more nodes or more than one hidden layer did not provide any improvement in performance. The network was trained for 2000 epochs resulting in a meansquared error (mse) of 6.4x10-7. Further training did not seem improve performance. A comparison between the neural network results and those by direct calculation is shown in table II. Fig. 4 shows the architecture of the neural network. This network employs hyperbolic tangent activation functions to map the transistor parameters to the values of the resistors.

Note that the number of patterns changes with all of the training and testing scenarios.This occurs because as the values of the biasing resistors change, the number of the voltage gains and values of Vce change, and one or the other can fall out of the ranges specified earlier. Only those that fall within those ranges are employed in the tests.When using the resistance values illustrated in table I the output parameters have the ranges shown in table III. It is not required that these ranges be followed precisely but it is likely a good practice to stay within them when considering an input set. The training set was included for comparative purposes.  It is important to realize that not all input parameter combinations are feasible. For example, if the Year 2016 ( ) D base bias resistors are kept to a low value the collector and emitter currents can be greater, resulting in a smaller value of Vce. In this case it would not be appropriate to set a small value of dc input resistance and a large value of Vce, since they can be mutually exclusive. However, by judiciously choosing realistic inputs the results can be close to the desired values. Some examples are shown in table IV. The requested parameters are shown with the percent error between the network output and the calculated values. By "tuning" the input parameters the percent errors can be reduced to acceptable values. In this case the voltage gain was the main focus. The resistor values from the last trial from table IV were used in a P-Spice simulation. The values were Rb1=30.0 k?,Rb2=15.24 k?, Rc=995 ?, and Re=730 ?. The results are summarized in table V along with the percent errors. 


# IV. Using A Finite Bypass Capacitor

If the bypass capacitor does not have zero impedance the problem is much more realistic, but requires a significant amount of additional work to analyze. Here, rather than using the hybrid -? model it is more appropriate to use the T-model since it is easier to include the emitter impedance. This is illustrated in Fig. 5 Figure 5: The T-model is used here in order to address the finite bypass capacitance Cb

The circuit was analyzed by employing nodal analysis at the three essential nodes with an input function of I amps at 3 kHz in order to determine the input impedance and other parameters.

After simplifying the expressions, three equations in three unknowns were used to determine Rin, and Av. Note that the impedance of the capacitor was only evaluated in magnitude, since the phase would have little effect on the overall result. The three nodal equations are listed here in (13).

The input impedance was evaluated as
amps I v R in 1 =
, and the gain was calculated as
1 3 v v A v = .
Once this was completed a current source was applied to the output to find the output impedance, resulting in the following simultaneous equations. 
I r g v g r R R v e m m e b b = ? ? ? ? ? ? ? + ? ? ? ? ? ? ? + + 1 1 1 1 2 2 1 1 (13a) 0 1 1 1 1 1 3 2 1 = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? + + + ? ? ? ? ? ? ? o o E e e r v r j C R r v r v ? (13b) [ ] 0 1 1 1 3 2 1 = ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? + C o o m m R r v r g v g v (13c)

# Global
I r R v g r v g v o C m o m = ? ? ? ? ? ? + + + ? ? ? ? ? ? ? ? + 1 1 1 3 2 1 (14a) 0 1 1 1 1 1 3 2 1 = ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + + ? + + ? ? ? ? ? ? ? o e E o e r v r R j C r v r v ?(14b)
After setting the source to zero the resulting output impedance was calculated as . In order to achieve the necessary parameters it required two 3x3 matrix inversions per iteration and convergence took significantly longer than when considering the ideal bypass capacitor, requiring roughly 3000 epochs. Increasing the number of epochs beyond that number did not improve performance in any measurable way. There were 10 trials for the bypass capacitors from 10µF to 100µF as illustrated in table VI. At first it seemed like the capacitors could be incorporated in the original design as an output parameter of the network along with the resistances but since only the magnitudes of the not really a problem because the necessary parameters for each topology can be learned by the network in a matter of minutes and the value of the bypass capacitor is not that critical when only 10 µF increments are being considered. The input frequency of 3 kHz was chosen since this is a good mid-band parameter for audio signals. Requiring the input frequency to be a variable caused problems with convergence, so for the present it was fixed at the aforementioned value. Finite values of bypass capacitance are rarely studied in undergraduate electronics courses, where most curricula assume that the bypass capacitor is ideal with infinite capacitance. This makes the analysis much simpler but not very realistic unless the capacitor used in the physical circuit is fairly large in value. It is interesting, and obvious, that as the capacitance increases, the results from the second design merge with those from the first one. This includes the training errors for each scenario. Table VII contains the results starting with a 10?F bypass capacitor, and ending with 100?F.It lists the solutions from P-Spice and compares them with the outputs from the neural network. For comparative purposes, the input parameters were kept the same as approach those yielded from the ideal bypass capacitor Having the capacitor impedance and the emitter resistance combined resulted in an overall impedance this reason 10 trials, one for each capacitor value, were conducted to provide proper training. Actually, this is that could not be resolved into separate elements. For in the last line in table IV. Here it is seen that at lower capacitances the voltage gain is lower and the input impedance higher, which one would expect. As the capacitance increases the results from the network approximation, which one would also expect. In this table the value of Vce is not listed since it is not dependent on the value of the bypass capacitor and remains constant.

It is noteworthy that once a capacitance of 60 -70?F is reached there is little change in the parameters of interest.
3![Figure 3 : This is the ac equivalent circuit of the common emitter amplifier with an ideal bypass capacitor](image-2.png "Figure 3 :")
![the emitter current is (? + 1)ib it is easy to figure that the resistance seen at the base is ( ) Neural Network Approach to Transistor Circuit Design](image-3.png "A")
1![Figure 1: Common emitter amplifier circuit](image-4.png "Figure 1 :")
4![Figure 4: Architecture of the neural network with 18 hidden nodes](image-5.png "Figure 4 :")
1![Journal of Computer Science and Technology Volume XVI Issue I Version I Neural Network Approach to Transistor Circuit Design [ ]](image-6.png "1 DA")
![Approach to Transistor Circuit Design impedances were considered this presented a problem.](image-7.png "")
1ResistorStart ValueStep ValueStop ValueRb16 k?250?10 k?Rb24 k?250?7 k?Rc1 k?100?3 k?Re400?100?1.5 k?
2UpperLowerCollectorEmitterNumberbasebaseresistorresistorData typeofresistorresistorRcRepatternsRb1Rb2(mse)(mse)(mse)(mse)Training set5439112580.2750.457Test Set 1 630693450.2020.288Test Set 2 1087593450.2020.286Test Set 3 1742786420.2060.292Test Set 4 2153486420.2060.294
3ParameterMinimum ValueMaximum ValueRin566 ?1.67 k?Ro947 ?2.18 k?Av-210 v/v-92 v/vVce2.41 v9.11 v
4Rin%Ro%Av%Vbe%(?)error(?)errorerrorerror900 -4.13 960-0.65 -172 -5.107.08.48880 -4.27 960-0.66 -172 -2.857.05.38880 -6.03 960-0.76 -172 -0.847.0-0.84
5ParameterNeural NetworkP-Spice% differenceRin827 ?804 ?0.37Ro953 ?881 ?2.5Av-170 v/v-180 v/v5.8Vce5.671 v5.56 v2.0
6Capacitor Value in ?FNumber of patternsUpper base resistor Rb1 (mse)Lower base resistor Rb2 (mse)Collector resistor Rc (mse)Emitter resistor Re (mse)10142943892182.171.8420135004372643.441.8739119824902472.221.804010652403219.0372.12508884121650.081.36608541117590.191.1370824456400.140.38807987197670.561.25907920177720.710.741007843148580.110.57
			( ) © 2016 Global Journals Inc. (US) 1
			© 2016 Global Journals Inc. (US)
		
		
			

## V. Conclusions And Further Work

This has been an interesting and rewarding research project. It is hoped by this author that engineers and faculty members will find these results useful. The fascinating part of this project comes particularly from the results of including the non-ideal bypass capacitance. Non-ideal bypass capacitors are rarely emphasized when teaching about, or working with, transistor circuits, at least at the introductory level. This neural network paradigm should be useful to engineers and faculty members when looking for solutions to various designs. The approach described in this paper can resolve and verify several transistor designs and illustrates the efficacy of neural networks as a development tool for amplifier circuit biasing. An extension of this work will be to expand this technique to other amplifier circuits, e.g., the common collector and common base models employing both the BJT and the MOSFET. An additional objective is to determine a set of input parameters that will yield accurate results without having to adjust them as illustrated in table IV.
			
			

				


* 
	
		Understanding Transmission Line Impedance Matching Using Neural Networks and PowerPoint
		
			TLHemminger
		
	
	
		Frontiers in Education
		
			T4E
			2005
		
	




* 
	
		Adaptive Pattern Recognition and Neural Networks
		
			YPao
		
		
			H
		
		
			1989
			Addison-Wesley
		
	




* 
	
		Principles of Artificial Neural Networks
		
			DGraupe
		
		
			2013
			World Scientific
		
	




* 
	
		Neural Network Design
		
			MTHagan
		
		
			HDemuth
		
		
			B
		
		
	
	Second Ed




* 
	
		Neural Network Toolbox
		
			HTDemuth
		
		
			MBeale
		
		
			The Mathworks Inc
		
	




* 
	
		References Références Referencias
		
	




* 
	
		Microelectronic Circuits
		
			ASSedra
		
		
			KCSmith
		
		
			2015
			Oxford University Press
		
	
	Seventh Ed




* 
	
		Microelectronic Circuit Design
		
			RCJaeger
		
	
	
		Mc Graw-Hill
		
			13
			1997