Reduction of Power Consumption using Different Coding Schemes using FPGA in NOC

Authors

  • Mitkari Sneha U.

  • Prof. Dr. S. S. Chorage

Keywords:

FPGA, LUTs, Network-on-Chip (NoC), System-on-Chip (SoC), Spartan 3E, VHDL

Abstract

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How to Cite

Mitkari Sneha U., & Prof. Dr. S. S. Chorage. (2017). Reduction of Power Consumption using Different Coding Schemes using FPGA in NOC. Global Journal of Computer Science and Technology, 17, 39–43. Retrieved from https://computerresearch.org/index.php/computer/article/view/1606

 
Reduction of Power Consumption using Different Coding Schemes using FPGA in NOC

Published

2017-01-15

Issue

Vol. 17 No. (2017): GJCST-A Hardware

Section

Articles

License

Copyright (c) 2017 Authors and Global Journals Private Limited

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.