# I. Introduction Design density and total length of interconnection wires are directly proportional with each other. This affects on long distant transmission delay and higher power consumption. # II. Related Work Giuseppe Ascia, et al. [1], In this paper, we propose the data encoding techniques are used to reduce both power dissipation and energy consumption of NoC links Working on the basis of end-to-end, the proposed encoding scheme exploits the wormhole switching techniques. That is, encoding and decoding of flits by NIs at source and destination. Shivaraj MN, et al. [2], Jeeva Anusha,et al. [3], In the proposed system, different encoding schemes are given. Also, hardware design properties are presented. Output details and power details are given. # III. Proposed System In method 1, Encoding is done by reducing number of type-I, II transitions and converting them to type-III and / or Type IV transition. Network-on-Chip power dissipation sources (links) [1] s process technology scaling continues number of transistor increases and hence power consumption also increases. Chip-multiprocessor can reach higher efficiency due to synchronized parallel execution of multiple programs or threads. Network-on-Chip is a scalable alternative to conventional when core count is more in Chip-multiprocessor. For mainly in current VLSI design, power efficiency is very important constraint in NoC design. In this paper, encoding techniques are used to reduce dynamic power reduction than previous system. Coupling switching activities are reduced. Detailed process of inversion is explained with the help of flowchart. Author ? ?: Electronics and telecommunication, Department Bharati Vidyapeeth's College of Engineering for Women Pune, 43 , Savitribai Phule Pune University, Maharashtra, India. e-mails: suvarna.chorage@bharatividyapeeth.edu, snehamitkari@gmail.com Here, capacitance is in µF. So, it is very negligible. ( ) (3)2 From ( 2) and ( 4), From ( 2) and ( 7), We know energy formula with respect to voltage and capacitance. These two formulae are the basic formulae for energy and power. ? As shown in Table .2, number of logics increases efficiency. As number of signals decreases power consumption also decreases from scheme-1to scheme-3. ? In previous system, for only one stage, i.e. Gray Encoding block, dynamic power consumption was 0.3mW.And now, in the present system after summing for all stages, dynamic power consumption is 0.46mW.From this comparison is done. We can conclude that power consumption is minimized in more amounts. W = (1/2)(???? 2 ) P = W/t W = VIt W/t = VIt /t = VI P = VI W/t = (1/2)(???? 2 )/t 1/2 (???? 2 )f = P P = (1/2)(?????? 2 ) # VI. Results and Discussion a) Scheme-I In scheme-I, half invert and full invert is performed. In full invert, 00 is converted into 11. When any one of the two is performed then inversion bit is set to 1, otherwise it is set to 0. # b) Scheme-II Simulation is done on Xilinx 14.5 ISE simulator. It is backend design tool. In scheme-II odd inversion is added. Type-II transitions are converted into type-IV transitions. Data coming at Network interface is from Encoder block. Then it is converted into desired encoded data which is passed through number of routers. This type of encoding is of scheme-II. # c) Scheme-III In scheme-III, there is additional inversion is performed that is Even inversion. For that Te block is added in second stage. Here, power consumption will be less than Scheme-II because; link power consumption is minimized in more amounts. Binary bit has some switching problem. So, they are converted into gray bits. # d) Results obtained by LCD Interfacing To calculate report for power consumption, first, we have to interface encoder and decoder with LCD. On this LCD, we can see desired output for both stages, encoding and decoding. Here, 'en' is for enable, 'clk' is for clock and 'rs' is for register select. When there is initialization of lcd rs=0. When rs=1, data is as it is written on lcd. When en=1, module is enabled or is started. # VII. Conclusion ? Encoding and decoding operation is used for security purpose. But here, main aim is to reduce power consumption in a effective way. ? Hardware part is used in such a way that cost of Spartan 3E (for Xilinx) is the lowest among different FPGA families. ? Dynamic power consumption without interfacing is calculated and compared with previous systems. ? In scheme-I, II, III, on the basis of parameters, power analysis is done. # A Reduction of Power Consumption using Different Coding Schemes using FPGA in NoC 2![Fig. 2: Block Diagram of Encoding Scheme-I In method-2, Full and odd inversions are done to convert type-II to type-IV transitions.](image-2.png "Fig. 2 :") ![](image-3.png "A") 1![Fig. 1:](image-4.png "Fig. 1 :") ![Encoding Scheme-II In this method-3, Even inversion is added with odd inversion. Because, Type-II transitions are formed in even inversion. Block Diagram of Encoding Scheme-III IV. Hardware Part Xilinx SPARTAN 3E FPGA kit: ? World's lowest cost FPGA is of Spartan 3E FPGA. ? Designed for the High-Volume Market ? Designed for the Low-Cost Market ? Optimized for Gate-Centric Designs ? 100K to 1.6 million gates ? 4000 LuTs. ? Lowest cost per logic ? Advanced 90nm technology.](image-5.png "") 5![Fig. 5: Design properties in Xilinx simulator](image-6.png "Fig. 5 :") 6![Fig. 6: Power analysis for scheme-III](image-7.png "Fig. 6 :") 344![Fig. 3:](image-8.png "Fig. 3 :Fig. 4 :Fig. 4 :") 478910![Fig. 7:](image-9.png "A 4 ]Fig. 7 :Fig. 8 :Fig. 9 :Fig. 10 :") 12![Fig. 12: Result of Last Stage](image-10.png "Fig. 12 :") 15![Fig. 15: Result for Scheme-1 LCD interfacing](image-11.png "Fig. 15 :") 17![Fig. 17: Result for Scheme-3 LCD interfacing](image-12.png "Fig. 17 :") 2ParameterScheme-1Scheme-2Scheme-3FamilySpartan-3ESpartan-3ESpartan-3EDeviceXC3S500E XC3S500E XC3S500EPackagePQ208PQ208PQ208Speed555Clock111Logics148163144Signals197177175IOs201120Dynamic Power0.46mW0.46mW0.46mWStatic Power13.69mW13.69mW13.69mW ( ) © 2017 Global Journals Inc. (US) 1 © 2017 Global Journals Inc. (US) * Giuseppe Ascia, Fabrizio Fazzino and Vincenzo Catania Data Encoding Schemes in Networks on Chip by Maurizio Palesi may 2016 30 * Dynamic Power Reduction in NOC by Encoding Techniques MNShivaraj HRavi Talawar IJIRST (International Journal for Innovative Research in Science & Technology) 2 04 September 2015 * Article 06596 VJeeva Anusha "Thrimurthulu Vlsi Of Low Modeling Network Chip International Journal of VLSI and Embedded Systems (IJVES) June 2015 06 * Data Encoding Schemes in Networks on Chip MaurizioAscia Fabrizio Fazzinoand VincenzoCatania IEEE transaction on computer aided design of integrated circuits and systems 30 5 may 2016 * Data Encoding Schemes for Reducing Energy Consumption in NoC NimaJafarzadeh MaurizioPalesi AhmedKhademzadeh AliAfzali-Kusha IEEE transaction on VLSI system march 2014 22 * Data Driven Data Encoding for Low Power Application SureshDannana GovindaRao Tamminaina AR VKumar Image Processing and Pattern Recognition(IPPR) 2015 8 * Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip AkulaSoujanya .PMrs Vinitha .KMr Gopi International Journal of Eminent Engineering Technologies 4 2 NOV 2015 * Power Consumption in Networkon-Chip by Encoding Scheme AVManoj SBhavya Sree KKumar VPurandharReddy International Journal of Innovative Research & Development (IJIRD) 3 January. 2014 * Data Encoding Techniques for Lower Power Dissipation in NoC DAnisha RSarathbabu International Journal of Engineering Research & Technology( IJERT) 3 February -2014 * ENCODING SCHEMES FOR POWER REDUCTION IN NETWORK ON CHIP LINKS SChetan Behere Somulu Gugulothu International Journal of Research in Engineering and Applied Sciences 02 2 July 2014 IJREAS)