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\title{Reduction of Power Consumption using Different Coding Schemes using FPGA in NoC}
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\begin{document}

             \author[1]{Mitkari Sneha  U.}

             \author[2]{Prof. Dr. S. S.  Chorage}

             \affil[1]{  Bharati vidyapeeth's college of engineering for Women, Katraj,Pune-43. }

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\date{\small \em Received: 9 December 2016 Accepted: 31 December 2016 Published: 15 January 2017}

\maketitle


\begin{abstract}
        


Network-On-Chip (NoC) is used as a main part of a system. NoC overcomes traditional System-On-Chip (SoC) problems. Because, SoC has problems like cost, design risk, more complexity and more power consumption. In software part, Xilinx ISE Design suite 14.5 with VHDL programming is used. It is simple programming language. In hardware part, FPGA of Spartan 3E family is used. It is advanced 90nm technology. It is world?s the cheapest FPGA family. It has 500K gates and 40 LUTs. It has lowest cost per logic. Its better advantage is that it is designed for more volume-to-market. Power consumption of given system is compared with previous system. From output power analysis chart, it is concluded that given system has lower power consumption than previous system. Power consumption of gray to binary conversion block of previous system is nearly equal to power consumption of present (given) whole system. This proves that there is a great reduction in power consumption in the system.

\end{abstract}


\keywords{FPGA, LUTs, Network-on-Chip (NoC), System-on-Chip (SoC), Spartan 3E, VHDL.}

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\let\tabcellsep& 	 	 		 
\section[{I. Introduction}]{I. Introduction}\par
Design density and total length of interconnection wires are directly proportional with each other. This affects on long distant transmission delay and higher power consumption. 
\section[{II. Related Work}]{II. Related Work}\par
Giuseppe Ascia, et al. \hyperref[b0]{[1]},\par
In this paper, we propose the data encoding techniques are used to reduce both power dissipation and energy consumption of NoC links Working on the basis of end-to-end, the proposed encoding scheme exploits the wormhole switching techniques.\par
That is, encoding and decoding of flits by NIs at source and destination. Shivaraj MN, et al. \hyperref[b1]{[2]}, Jeeva Anusha,et al. \hyperref[b2]{[3]},\par
In the proposed system, different encoding schemes are given. Also, hardware design properties are presented. Output details and power details are given. 
\section[{III. Proposed System}]{III. Proposed System}\par
In method 1, Encoding is done by reducing number of type-I, II transitions and converting them to type-III and / or Type IV transition. Network-on-Chip power dissipation sources (links) \hyperref[b0]{[1]} s process technology scaling continues number of transistor increases and hence power consumption also increases. Chip-multiprocessor can reach higher efficiency due to synchronized parallel execution of multiple programs or threads. Network-on-Chip is a scalable alternative to conventional when core count is more in Chip-multiprocessor. For mainly in current VLSI design, power efficiency is very important constraint in NoC design.  In this paper, encoding techniques are used to reduce dynamic power reduction than previous system. Coupling switching activities are reduced. Detailed process of inversion is explained with the help of flowchart.\par
Author ? ?: Electronics and telecommunication, Department Bharati Vidyapeeth's College of Engineering for Women Pune, 43 , Savitribai Phule Pune University, Maharashtra, India. e-mails: suvarna.chorage@bharatividyapeeth.edu, snehamitkari@gmail.com    Here, capacitance is in µF. So, it is very negligible.\par
() (3)\textbf{2}\par
From ( \hyperref[formula_0]{2}) and ( 4),\par
From ( \hyperref[formula_0]{2}) and (  {\ref 7}),\par
We know energy formula with respect to voltage and capacitance.\par
These two formulae are the basic formulae for energy and power. ? As shown in Table  {\ref .}2, number of logics increases efficiency. As number of signals decreases power consumption also decreases from scheme-1to scheme-3. ? In previous system, for only one stage, i.e. Gray Encoding block, dynamic power consumption was 0.3mW.And now, in the present system after summing for all stages, dynamic power consumption is 0.46mW.From this comparison is done. We can conclude that power consumption is minimized in more amounts.W = (1/2)(???? 2 ) P = W/t W = VIt W/t = VIt /t = VI P = VI W/t = (1/2)(???? 2 )/t 1/2 (???? 2 )f = P P = (1/2)(?????? 2 ) 
\section[{VI. Results and Discussion}]{VI. Results and Discussion}\par
a) Scheme-I In scheme-I, half invert and full invert is performed. In full invert, 00 is converted into 11. When any one of the two is performed then inversion bit is set to 1, otherwise it is set to 0. 
\section[{b) Scheme-II}]{b) Scheme-II}\par
Simulation is done on Xilinx 14.5 ISE simulator. It is backend design tool. In scheme-II odd inversion is added. Type-II transitions are converted into type-IV transitions. Data coming at Network interface is from Encoder block. Then it is converted into desired encoded data which is passed through number of routers. This type of encoding is of scheme-II. 
\section[{c) Scheme-III}]{c) Scheme-III}\par
In scheme-III, there is additional inversion is performed that is Even inversion. For that Te block is added in second stage. Here, power consumption will be less than Scheme-II because; link power consumption is minimized in more amounts.\par
Binary bit has some switching problem. So, they are converted into gray bits.  
\section[{d) Results obtained by LCD Interfacing}]{d) Results obtained by LCD Interfacing}\par
To calculate report for power consumption, first, we have to interface encoder and decoder with LCD. On this LCD, we can see desired output for both stages, encoding and decoding.\par
Here, 'en' is for enable, 'clk' is for clock and 'rs' is for register select. When there is initialization of lcd rs=0. When rs=1, data is as it is written on lcd. When en=1, module is enabled or is started. 
\section[{VII. Conclusion}]{VII. Conclusion}\par
? Encoding and decoding operation is used for security purpose. But here, main aim is to reduce power consumption in a effective way. ? Hardware part is used in such a way that cost of Spartan 3E (for Xilinx) is the lowest among different FPGA families. ? Dynamic power consumption without interfacing is calculated and compared with previous systems. ? In scheme-I, II, III, on the basis of parameters, power analysis is done. 
\section[{A}]{A}\par
Reduction of Power Consumption using Different Coding Schemes using FPGA in NoC   \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Fig. 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-3.png}
\caption{\label{fig_1}A}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Fig. 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-5.png}
\caption{\label{fig_3}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Fig. 5 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Fig. 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{344}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Fig. 3 :Fig. 4 :Fig. 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{478910}\includegraphics[]{image-9.png}
\caption{\label{fig_7}A 4 ]Fig. 7 :Fig. 8 :Fig. 9 :Fig. 10 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{12}\includegraphics[]{image-10.png}
\caption{\label{fig_8}Fig. 12 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{15}\includegraphics[]{image-11.png}
\caption{\label{fig_9}Fig. 15 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{17}\includegraphics[]{image-12.png}
\caption{\label{fig_10}Fig. 17 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.2763374485596708\textwidth}P{0.2518518518518518\textwidth}P{0.16090534979423868\textwidth}P{0.16090534979423868\textwidth}}
Parameter\tabcellsep Scheme-1\tabcellsep Scheme-2\tabcellsep Scheme-3\\
Family\tabcellsep Spartan-3E\tabcellsep Spartan-3E\tabcellsep Spartan-3E\\
Device\tabcellsep \multicolumn{3}{l}{XC3S500E XC3S500E XC3S500E}\\
Package\tabcellsep PQ208\tabcellsep PQ208\tabcellsep PQ208\\
Speed\tabcellsep 5\tabcellsep 5\tabcellsep 5\\
Clock\tabcellsep 1\tabcellsep 1\tabcellsep 1\\
Logics\tabcellsep 148\tabcellsep 163\tabcellsep 144\\
Signals\tabcellsep 197\tabcellsep 177\tabcellsep 175\\
IOs\tabcellsep 20\tabcellsep 11\tabcellsep 20\\
Dynamic Power\tabcellsep 0.46mW\tabcellsep 0.46mW\tabcellsep 0.46mW\\
Static Power\tabcellsep 13.69mW\tabcellsep 13.69mW\tabcellsep 13.69mW\end{longtable} \par
 
\caption{\label{tab_0}Table 2 :}\end{figure}
 			\footnote{( ) © 2017 Global Journals Inc. (US) 1} 			\footnote{© 2017 Global Journals Inc. (US)} 		 		\backmatter  			  				\begin{bibitemlist}{1}
\bibitem[Jeeva Anusha et al. (2015)]{b2}\label{b2} 	 		‘Article 06596’.  		 			V Jeeva Anusha 		,  		 			" Thrimurthulu 		,  		 			Vlsi 		,  		 			Of 		,  		 			Low 		,  		 			Modeling 		,  		 			Network 		,  		 			Chip 		.  	 	 		\textit{International Journal of VLSI and Embedded Systems (IJVES)},  				June 2015. 06.  	 
\bibitem[Dannana et al. ()]{b5}\label{b5} 	 		‘Data Driven Data Encoding for Low Power Application’.  		 			Suresh Dannana 		,  		 			Govinda Rao Tamminaina 		,  		 			A R V Kumar 		.  	 	 		\textit{Image Processing and Pattern Recognition(IPPR)},  				2015. 8 p. .  	 
\bibitem[Jafarzadeh et al. (2014)]{b4}\label{b4} 	 		‘Data Encoding Schemes for Reducing Energy Consumption in NoC’.  		 			Nima Jafarzadeh 		,  		 			Maurizio Palesi 		,  		 			Ahmed Khademzadeh 		,  		 			Ali Afzali-Kusha 		.  	 	 		\textit{IEEE transaction on VLSI system},  				march 2014. 22.  	 
\bibitem[Ascia and Catania (2016)]{b3}\label{b3} 	 		‘Data Encoding Schemes in Networks on Chip’.  		 			Maurizio Ascia 		,  		 			Fabrizio Fazzinoand Vincenzo Catania 		.  	 	 		\textit{IEEE transaction on computer aided design of integrated circuits and systems}  		may 2016. 30  (5) .  	 
\bibitem[Anisha and Sarathbabu (2014)]{b8}\label{b8} 	 		‘Data Encoding Techniques for Lower Power Dissipation in NoC’.  		 			D Anisha 		,  		 			R Sarathbabu 		.  	 	 		\textit{International Journal of Engineering Research \& Technology( IJERT)}  		February -2014. 3.  	 
\bibitem[Soujanya et al. ()]{b6}\label{b6} 	 		‘Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip’.  		 			Akula Soujanya 		,  		 			. P Mrs 		,  		 			Vinitha 		,  		 			. K Mr 		,  		 			Gopi 		.  	 	 		\textit{International Journal of Eminent Engineering Technologies}  		NOV 2015. 4  (2) .  	 
\bibitem[Shivaraj et al. (2015)]{b1}\label{b1} 	 		‘Dynamic Power Reduction in NOC by Encoding Techniques’.  		 			M N Shivaraj 		,  		 			H Ravi 		,  		 			Talawar 		.  	 	 		\textit{IJIRST (International Journal for Innovative Research in Science \& Technology)}  		September 2015. 2  (04) .  	 
\bibitem[Chetan et al. (2014)]{b9}\label{b9} 	 		‘ENCODING SCHEMES FOR POWER REDUCTION IN NETWORK ON CHIP LINKS’.  		 			S Chetan 		,  		 			Behere 		,  		 			Somulu 		,  		 			Gugulothu 		.  	 	 		\textit{International Journal of Research in Engineering and Applied Sciences}  		July 2014. 02 p. 2.  	 	 (IJREAS)) 
\bibitem[Giuseppe Ascia, Fabrizio Fazzino and Vincenzo Catania Data Encoding Schemes in Networks on Chip by Maurizio Palesi (2016)]{b0}\label{b0} 	 		‘Giuseppe Ascia, Fabrizio Fazzino and Vincenzo Catania’.  	 	 		\textit{Data Encoding Schemes in Networks on Chip by Maurizio Palesi},  				may 2016. 30.  	 
\bibitem[Manoj et al. (2014)]{b7}\label{b7} 	 		‘Power Consumption in Networkon-Chip by Encoding Scheme’.  		 			A V Manoj 		,  		 			S Bhavya Sree 		,  		 			K Kumar 		,  		 			V Purandhar Reddy 		.  	 	 		\textit{International Journal of Innovative Research \& Development (IJIRD)}  		January. 2014. 3.  	 
\end{bibitemlist}
 			 		 	 
\end{document}
