Abstract

Objectives: Multiple pipelines are used to enhance the throughput. Multiple data are fetched at pipeline and classified into different data by selecting and decoding appropriate bits in Instruction field. Methods/Statistical analysis: Enhancing the throughput is one of the important issue need to be considered in multitasking system. In the present system parallel pipeline is used to improve the data rate. The data rate further can be enhanced by doing classification before it feeding to pipeline. In the present system it is achieved by data classification which is done at each pipeline based upon mode selecting bits and operation codes. Findings: The decoded data from any program is fetched and send simultaneously to arithmetic logic unit or any output device simultaneously for further processing. The data is classified and separately passed through the stages of pipeline. Based on the type of the data present in the machine code the opcode is classified and separated. The classified data is passed through the pipeline to optimize the data throughput. The design of the circuit is implemented in Proteus simulation software. It is observed that the multi-byte data or instructions are classified and feed through the pipeline. The time gap between two sequential bytes is drastically reduced and found they are almost sent side by side. Application/Improvements: The present method can be used in digital systems and parallel processing systems where high speed data rates are required. The data rate further can be improved by increasing the number of stages in the pipeline.