FPGA Implementation of NPSF Testing Using Block Code Technique

Authors

  • K.L.V.Ramana Kumari

  • M. Asha Rani

  • N.Balaji

Keywords:

LFSR pattern generation, euler pattern generation, block code technique, Nexys 4 DDR Artix 7 FPGA

Abstract

This paper presents a test structure for high speed memories. Built in self test (BIST) give the solution for testing memories and associate hardware for test pattern generation and application for a variety of test algorithms. Memory test algorithm for neighborhood pattern sensitive faults (NPSF) is developed by using block code technique to identify the base cell and deleted neighborhood cells. Test pattern generation can be done by using LFSR and Euler pattern generation. The testing process is verified using Xilinx ISE 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.

How to Cite

K.L.V.Ramana Kumari, M. Asha Rani, & N.Balaji. (2018). FPGA Implementation of NPSF Testing Using Block Code Technique. Global Journal of Computer Science and Technology, 18(G3), 1–6. Retrieved from https://computerresearch.org/index.php/computer/article/view/1709

FPGA Implementation of NPSF Testing Using Block Code Technique

Published

2018-07-15