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\title{FPGA Implementation of NPSF Testing using Block Code Technique}
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             \author[1]{K.L.V.Ramana  Kumari}

             \author[2]{M. Asha  Rani}

             \author[3]{  N.Balaji}

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\date{\small \em Received: 7 December 2017 Accepted: 31 December 2017 Published: 15 January 2018}

\maketitle


\begin{abstract}
        


This paper presents a test structure for high speed memories. Built in self test (BIST) give the solution for testing memories and associate hardware for test pattern generation and application for a variety of test algorithms. Memory test algorithm for neighborhood pattern sensitive faults (NPSF) is developed by using block code technique to identify the base cell and deleted neighborhood cells. Test pattern generation can be done by using LFSR and Euler pattern generation. The testing process is verified using Xilinx ISE 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.

\end{abstract}


\keywords{LFSR pattern generation, euler pattern generation, block code technique, Nexys 4 DDR Artix 7 FPGA.}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
uilt in self test (BIST) design technique is a part of circuit which is used to test the circuit itself. Engineers design BISTs to satisfy demands such as lower repair cycle times or constraints such as limited technician accessibility and cost of testing during manufacture and high reliability. The main purpose of BIST is to reduce the test complexity, and thereby decrease the cost and reduce dependence upon external (pattern programmed) test equipment \hyperref[b0]{[1]}. Built in self test techniques are very useful in testing of logic circuits, because they offer a cost effective way to test complex digital devices. First the BIST concept was implemented on combinational circuits, after that it found quick demands in the testing of regular structures like programmable logic arrays, read only memories, and random access memories.\par
Quick increment of multifaceted nature in the integrated circuits has prompt impact following on memory testing. On one view, the limit of randomaccess memories upgrades, in this manner expanding the test time and cost, on the other view, the complexity of memory circuits becomes more, and therefore more failure modes and faults should be considered in order to get a product with good quality \hyperref[b3]{[4]}. Accordingly, different constraints need to take care while considering a test algorithm.\par
Minimizing the number of memory operations in order to allow large capacity memories to be tested in proper period of time and covering a larger collection of memory faults. In the last previous days of memory design test procedures were developed in an ad-hoc manner. The fault coverage of these ad-hoc test procedures was limited and often indeterminable \hyperref[b1]{[2]}. This shortcoming, acknowledged by most researchers, motivated the introduction of such fault models as stuck-at faults, decoder faults, coupling faults. If density of memory circuits increases, it increases coupling effects then the pattern sensitive fault PSF is becoming very important fault model \hyperref[b2]{[3]}.\par
The  
\section[{b) Neighborhoods Pattern Sensitive Faults}]{b) Neighborhoods Pattern Sensitive Faults}\par
A Pattern Sensitive Fault is a restrictive coupling fault in which the content of a memory cell, or the capacity to change its content, is affected by a specific bit pattern in different cells in the memory. Here the information maintenance and change of the victim cell are influenced by an arrangement of aggressor cells. A neighborhood pattern sensitive Fault (NPSF) is a special instance of pattern sensitive faults \hyperref[b7]{[8]}, wherein the affecting (coupling) cells are in the neighborhood of the impacted (coupled) cell. The coupled cell is known as the base (or victim) cell and the coupling cells are known as the deleted neighborhood cells. The neighborhood incorporates 4 deleted neighborhoods and one base cell. It forms the coupling of these 4 cells with the base cell considering effect as the NPSF fault modeling. 
\section[{c) Active NPSF}]{c) Active NPSF}\par
The base cell changes its contents because of changes in the deleted neighborhood pattern. To identify these affect, every cell must be read in state 0 and in state 1 for every single conceivable change in the deleted neighborhood pattern. There are two distinctive conceivable states for the base cell (0 and 1), N-1 methods for picking the deleted neighborhood cell which must experience one of two conceivable advances (? or â??"), and N-2 potential outcomes for the rest of the neighborhood cell contents.\par
2* (N-1)*2*2N-2 = (N-1)* 2N is the aggregate number \hyperref[b7]{[8]} of active neighborhood patterns (ANPs). It require 128 patterns for identifying active NPSF faults. For type-1 NPSF, 2 is base cell and 0, 1, 3 and 4 are deleted neighborhood cells.  
\section[{d) Passive NPSF}]{d) Passive NPSF}\par
The content of the base cell can't be changed because of a specific neighborhood pattern. Every cell must be written and read in state 0 and in state 1 for all changes of the deleted neighborhood pattern. For each of the 2N-1 deleted neighborhood patterns, the two conceivable advances ? and â??" must be confirmed. Subsequently, the aggregate number of PNPSFs is 2*2N-1=2N. Here N is number of cells. It require 32 test patterns for recognizing active NPSF faults. 
\section[{e) Static NPSF}]{e) Static NPSF}\par
The content of a base cell is compelled to a specific state because of a specific neighborhood pattern. To distinguish these faults, apply the 2N combinations of 0s and 1s to the N-cell neighborhood, and check by perusing every cell that each pattern can be stored. It varies from ANPSF that it is not necessary to have a change to transition to sensitize an SNPSF. We required 32 test patterns for recognizing static NPSF faults. Fig  {\ref 5} shows that the memory is divided into nine different blocks. Nine test cases are used for testing the memory since maximum size of the block is 9. For test case 1 each block of first cell is selected as base cell then the base cells are selected as 00, 03, 06, 30, 33, 36, 60, 63, 66 and the pattern are applied to the deleted neighborhood cells of each base cell. For test case 2 each block of second cell is selected as base cell then the base cells are selected 01, 04, 07, 31, 34, 37, 61, 64, and 67. Likewise for test case 9 the base cells are selected as 22, 25, 52 and 55. 
\section[{III.}]{III.} 
\section[{Memory Testing}]{Memory Testing} 
\section[{Fig. 5: 8*8 memory divides into blocks}]{Fig. 5: 8*8 memory divides into blocks}\par
If base cell positions are not available in blocks then the base cells are chosen based on their availability \hyperref[b9]{[10]}. Table \hyperref[tab_0]{1} shows the base cells according to their respective test case.  
\section[{c) Memory testing by using different test cases}]{c) Memory testing by using different test cases} 
\section[{d) Algorithm}]{d) Algorithm}\par
Step 1: Write all base cells to 1.\par
Step 2: Applying pattern to neighborhood cells  
\section[{e) Operation}]{e) Operation}\par
During the 1st operation, cell 1 of each block will be selected as a base cell and the corresponding    
\section[{b) Xilinx Reports}]{b) Xilinx Reports}\par
Xilinx ISE is a software tool is used for synthesis and analysis of HDL designs \hyperref[b10]{[11]}. Allows the developer to synthesize the design, gives timing analysis, RTL diagrams, and configure the target device with a programming kit.    The table \hyperref[tab_2]{2} shows the summary of device utilization for Nexys 4 DDR Artx 7 FPGA. The utilization of device gives the information of number of LUTs, logic blocks and number of bonded IOBS used in FPGA, it can be obtained from synthesis report generated by Xlinx ISE.\par
V. 
\section[{Conclusion and Future Scope}]{Conclusion and Future Scope}\par
For memory arrays, the excessive test algorithmic time associated with NPSF fault model. This paper presents a BIST implementation using block code technique to select base cells and deleted neighborhood cells of neighborhood pattern sensitive faults (NPSFs) in random access memories (RAMs). Testing process is synthesized and implemented on Nexys 4 DDR Artix 7 FPGA board. In order to improve the effectiveness of coupling faults, type-2 NPSFs can be modelled and tested.\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Fig. 1 :}\end{figure}
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\noindent\textbf{2}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Fig. 2 :}\end{figure}
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\noindent\textbf{34}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Fig. 3 :Fig. 4 :}\end{figure}
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\noindent\textbf{3}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Step 3 :}\end{figure}
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\noindent\textbf{6789}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Step 6 :Fig. 7 :Fig. 8 :Fig. 9 :}\end{figure}
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\noindent\textbf{6}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Fig. 6 :}\end{figure}
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\noindent\textbf{10}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Fig. 10 :}\end{figure}
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\noindent\textbf{11}\includegraphics[]{image-9.png}
\caption{\label{fig_7}Fig. 11 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{12}\includegraphics[]{image-10.png}
\caption{\label{fig_8}Fig. 12 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{}
\end{longtable} \par
 
\caption{\label{tab_0}Table 1 :}\end{figure}
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\noindent\textbf{2} \par 
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Year 2018\end{longtable} \par
 
\caption{\label{tab_2}Table 2 :}\end{figure}
 			\footnote{© 2018 Global Journals} 			\footnote{© 2018 Global Journals 1} 		 		\backmatter  			  				\begin{bibitemlist}{1}
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\end{document}
