@incollection{,
	
					
					
					57E22E5072A2367B4D0FEE58DC482060
				,
	author={{BhagyasriChandaka} and {MVGR college of engineering}},
	journal={{Global Journal of Computer Science and Technology}},
	journal={{GJCST}}0975-41720975-435010.34257/gjcst,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}18116
}

@incollection{b0,
	
	
		,
	title={{SOC test integration platform}}
		,
	author={{
			K CAuguslikifli
		} and {
			Wu
		}}
		
	
	
		,
	booktitle={{IEEE transaction on Very Large Scale Integration (VLSI)}}
				
			,
	year={2015}
			15
		
	

}

@incollection{b1,
	
	
		,
	title={{parameter specific ring oscillator for process monitor at the 45nm node}}
		,
	author={{
			LT NWang
		} and {
			NXu
		} and {
			SOToh
		} and {
			ARNeureuther
		} and {
			TJKingliu
		} and {
			BNikolic
		}}
		
		
		
		
		
	
	
		,
	journal={{Custom integration circuit conference}}
		
			,
	year={2010}
			,
	publisher={IEEE}
		
	

}

@book{b2,
	
	
		,
	title={{Statistical static timing Analysis". The VLSI journal, Integration}}
		,
	author={{
			CristianoForzan
		} and {
			DavidePandini
		}}
		
		
			,
	year={2009}
			42
		
	

}

@incollection{b3,
	
	
		,
	title={{Timing Model Extraction of Hierarchical Blocks by Graph Reduction}}
		,
	author={{
			WCho
		} and {
			Moon
		}}
		
	
	
		,
	booktitle={{Harish Kriplani and Krishna Belkhale}}
				
			,
	year={2002}
			
		
	
	,
	note={Proc. Design Automation Conference}

}

@incollection{b4,
	
	
		,
	title={{Ring Oscillators for CMOS Process Tuning and Variability Control}}
		,
	author={{
			MBhushan
		} and {
			AGattiker
		} and {
			MBKetchen
		} and {
			KKDas
		}}
		
		
		
	
	
		,
	journal={{In IEEE Trans. on Semiconductor Manufacturing}}
		
			1
			1
			
			,
	year={Feb. 2006}
		
	

}

@incollection{b5,
	
	
		,
	title={{Systemon-chip Reuse and Integration}}
		,
	author={{
			RSaleh
		} and {
			SWilton
		} and {
			SMirabbasi
		}}
		
		
	
	
		,
	booktitle={{Proceedings of IEEE}}
				IEEE
		
			,
	year={2006}
			94
		
	

}

@book{b6,
	
	
		,
	title={{Time-domain macro models for VLSI interconnect analysis}}
		,
	author={{
			NSeok-Yoon Kim
		} and {
			LTGopal
		} and {
			Pillage
		}}
		
		
		
			,
	year={1994}
			13
		
	

}

@book{b7,
	
	
		,
	title={{Static timing analysis for modelling QoS in Network-on-chip}}
		,
	author={{
			IsaacEvgenikrimer
		} and {
			Keslassey
		} and {
			Avinoamkoladny
		} and {
			MattanerezLsaskharwalter
		}}
		
		
		
		
			,
	publisher={Elsevier}
			71
		
	

}

@book{b8,
	
	
		,
	title={{Timing analysis of network on chip architectures for MP-SOC platforms}}
		,
	author={{
			ParthapratinpandeCristiangrecu
		} and {
			AndreLvanov
		} and {
			ResSaleh
		}}
		
		
		
			,
	year={2005}
			,
	publisher={Elsevier}
			36
		
	

}