@incollection{,
	
					
					
					AACB383353AF37C892F69EE75E072889
				,
	author={{AdeshKumar} and {PoojaNagwal} and {Dhirendra SinghGangwar} and {University of Petroleum and Energy Studies Dehradun, India}},
	journal={{Global Journal of Computer Science and Technology}},
	journal={{GJCST}}0975-41720975-435010.34257/gjcst,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}13119
}

@incollection{b0,
	
	
		,
	title={{FPGA Based Efficient Implementation of Viterbi Decoder}}
		,
	author={{
			AnubhutiKhare
		} and {
			ManishSaxena
		} and {
			JagdishPatel
		}}
		
		
	
	
		,
	journal={{International Journal of Engineering and Advanced Technology}}
		
			,
	year={October 2011}
		
	

}

@book{b1,
	
	
		,
	title={{Encoding with repeater Insertion for Minimizing delay in VLSI interconnects}}
		,
	author={{
			CRaghunandan
		} and {
			KSSainarayanan
		} and {
			MBSrinivas
		}}
		
		
		
			,
	year={2006}
			,
	publisher={IEEE}
		
	

}

@incollection{b2,
	
	
		,
	title={{M "design and Implementation of Viterbi Encoder and Decoder Using FPGA}}
		,
	author={{
			AMChitra
		} and {
			RoopaAshwath
		}}
		
	
	
		,
	journal={{International Journal of Engineering and Advanced}}
		
			,
	year={june 2012}
		
	

}

@book{b3,
	
	
		,
	title={{Temporal Coding Schemes for Energy Efficient Data Transmission in Systems-onchip}}
		,
	author={{
			GeorgeKornaros
		}}
		
	

}

@book{b4,
	
	
		,
	title={{Energy Efficient Spatial coding Technique for Low power VLSI Application" the 6th International Workshop on System on Chip for Real Time Appilication}}
		,
	author={{
			JV RRavindra
		} and {
			NavyaChittavu
		} and {
			MBSrinivas
		}}
		
		
		
			,
	year={2006}
			,
	publisher={IEEE}
		
	

}

@book{b5,
	
	
		,
	title={{An efficient power reduction technique for low power data I/O for military appilication}}
		,
	author={{
			JV RRavindra
		} and {
			KSainarayanan
		} and {
			MBSrinivas
		}}
		
		
		
			,
	year={2005}
		
	

}

@incollection{b6,
	
	
		,
	title={{Delay and Power Minimization in VLSI Interconnects with Spatio-temporal Bus-Encoding Scheme}}
		,
	author={{
			KSSainarayanan
		} and {
			CRaghunandan
		} and {
			MBSrinivas
		}}
		
		
	
	
		,
	journal={{IEEE Computer Society Annual Symposium on VLSI}}
		
			,
	year={2007}
		
	

}

@book{b7,
	
	
		,
	title={{Minimizing Simulation Switching Noise (SSN) using Modified Odd/even Bus Invert Method" third IEEE international Workshop on Electronic design, test and appilications}}
		,
	author={{
			KSSainarayanan
		} and {
			JV RRavindra
		} and {
			MSrinivas
		}}
		
		
		06) 0-7695- 2500-8/05$20.00
		
			,
	year={2005}
			,
	publisher={IEEE}
		
	

}

@book{b8,
	
	
		,
	title={{Efficient Spatial-Temporal Coding Scheme for Minimizing Delay in Interconnects}}
		,
	author={{
			KSSainarayanan
		} and {
			CRaughunandan
		} and {
			MBRavindra
		} and {
			Srinivas
		}}
		
		
		
		
			,
	year={2006}
			,
	publisher={IEEE}
		
	

}

@book{b9,
	
	
		,
	title={{Coding for Minimizing Energy in VLSI Interconnects}}
		,
	author={{
			KSSainarayanan
		} and {
			JV RRavindra
		} and {
			KiranTNath
		} and {
			MSrinivas
		}}
		
		
		
		
			,
	year={2006}
			,
	publisher={IEEE}
		
	

}

@incollection{b10,
	
	
		,
	title={{Error -Correction and Crosstalk Avoidance in DSM buses}}
		,
	author={{
			NKetan
		} and {
			IgorLPatel
		} and {
			Markov
		}}
		
		
	
	
		,
	journal={{IEEE transactions on VLSI systems}}
		
			12
			10
			,
	year={October 2004}
		
	

}

@book{b11,
	
	
		,
	title={{A Novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects}}
		,
	author={{
			KSSainarayan
		} and {
			JV RRavindr
		} and {
			MSrinivas
		}}
		
		
		
			,
	year={2006}
			,
	publisher={IEEE}
		
	

}

@incollection{b12,
	
	
		,
	title={{A novel encoding scheme for delay and energy minimization in VLSI Interconnect with Built-In Error Detection}}
		,
	author={{
			MLingamneni Avinash
		} and {
			MBKrishna
		} and {
			Srinivas
		}}
		
		
	
	
		,
	journal={{IEEE Computer Society Annual Symposium on}}
		
			,
	year={2008}
		
	

}

@incollection{b13,
	
	
		,
	title={{Bus-Invert Coding for Low-Power I/O}}
		,
	author={{
			RMircea
		} and {
			WaynePStan
		} and {
			Burleson
		}}
		
		
	
	
		,
	journal={{IEEE Transaction on VLSI}}
		
			,
	year={1995}
		
	

}

@incollection{b14,
	
	
		,
	title={{Modeling Techniques for Energy-Efficient System-on -a chip signaling}}
		,
	author={{
			MIsmail
		} and {
			NTan
		}}
		
	
	
		,
	journal={{IEEE Circuits and Magazine}}
		
			,
	year={2003}
		
	

}

@book{b15,
	
	
		,
	title={{Communication Systems Analog & Digital" Chapter}}
		,
	author={{
			RPSingh
		} and {
			&SSapre
		}}
		
		
			11
			
		
	

}