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\title{Comparative Analysis of Spatio and Viterbi Encoding and Decoding Techniques in Hardware Description Language}
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             \author[1]{Adesh  Kumar}

             \author[2]{Pooja  Nagwal}

             \author[3]{Dhirendra Singh  Gangwar}

             \affil[1]{  University of Petroleum and Energy Studies Dehradun, India}

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\date{\small \em Received: 10 December 2012 Accepted: 4 January 2013 Published: 15 January 2013}

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\begin{abstract}
        


The paper focuses on the design and synthesis of hardware chip for Spatio and Viterbi encoding and decoding techniques. Both techniques are used for digital data encoding and decoding in transmitter and receiver respectively. These techniques are used for error control coding found in convolution codes. Spatio coding is also used to eliminate crosstalk among interconnect wires, thereby reducing delay. The encoded data is in packet form may be of ?N? bits. Data is decoded at different clock pluses at which it is encoded. A comparative analysis is done for hardware parameter, timing parameters and device utilization. Design is implemented in Xilinx 14.2 VHDL software, and functional simulation was carried out in Modelsim 10.1 b, student edition. Hardware parameters such as size cost and timings are extracted from the design code.

\end{abstract}


\keywords{field programmable gate array (FPGA), register transfer level (RTL), very high speed integrated circuit hardware description language (VHDL), very lar}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
he Viterbi Algorithm \hyperref[b0]{[1]} [3] \hyperref[b15]{[16]} is used widely for estimation and detection problems in digital communication and signal processing. It is used to detect signals in communication channels with memory \hyperref[b2]{[3]}, and to decode sequential error control codes \hyperref[b15]{[16]} that are used to improve the performance of digital communication systems. During the transmission or storage process, the digital data may get corrupted due to noise. Channel coding \hyperref[b0]{[1]} is a method to encode the data in a manner that it can be recovered even if it gets influenced by noise .Channel Coding involves adding redundant bits \hyperref[b2]{[3]} to the data so that when it gets corrupted due to noise, the data can still be recovered through the redundancy \hyperref[b0]{[1]} present in it. Block codes and convolution codes \hyperref[b15]{[16]} are two major forms of Channel coding. The block codes \hyperref[b15]{[16]} transform a block of k symbols into a block of n symbols called code word, where n > k. Since the output n-symbol code word depends only upon the corresponding k-symbol input code word, the encoder is memory less and can be implemented in a combinational logic. On the other hand, a Viterbi encoder \hyperref[b2]{[3]}  \hyperref[b15]{[16]} not only depends on the corresponding k-symbol input block but also on m previous input blocks. Viterbi encoders are implemented in sequential logic because they are associated with memory element. Keeping in mind the essentials of communication channels in wireless systems, reliable data communication, fast as well as accurate is the main requirement and Viterbi coding helps us in achieving the same. The Viterbi algorithm \hyperref[b0]{[1]} applies the maximum-likelihood path  {\ref [3] [16]} method for error detection. The most common metric used is the branch distance metric \hyperref[b0]{[1]}. This is basically the dot product between the received codeword and the allowable codeword \hyperref[b15]{[16]}. These metrics are cumulative so that the path with the largest total metric is the final desired output. The selection of survivor path basically determines the whole of the Viterbi algorithm and ensures that the algorithm completes with the maximum likelihood path \hyperref[b0]{[1]}. The algorithm ends and is completed when all of the nodes in the trellis have been labeled and their entering survivor paths have been determined. The design space for VLSI implementation of Viterbi decoders is large, involving choices of throughput, latency, area, and power. Even for a fixed set of parameters like constraint length, encoder polynomials \hyperref[b2]{[3]} and trace-back depth \hyperref[b0]{[1]}, the task of designing a Viterbi decoder is quite complicated and requires significant effort. Sometimes, due to incomplete design space exploration or incorrect analysis, a suboptimal \hyperref[b2]{[3]} design is selected In onchip interconnects \hyperref[b1]{[2]} [4], there is propagation delay \hyperref[b4]{[5]} due to resistance and inter wire interconnects and gates and some others sources are such as alpha particles, electromagnetic interference \hyperref[b1]{[2]} and power grid fluctuation \hyperref[b7]{[8]}. Various techniques are used to minimize the delay and also various error detection and correction scheme \hyperref[b5]{[6]}. In this paper, a Spatio-temporal bus encoding scheme \hyperref[b1]{[2]} [4] [5] \hyperref[b8]{[9]} is proposed which are reduced the delay due to its optimized hardware parameters and implementation. Experimental results of this scheme is show that this scheme perform better and have advantages of error detection, also in this paper we compare this scheme with Viterbi encoding scheme.  
\section[{Year}]{Year}\par
The rest of this paper is organized as follow. The algorithm of Spatio temporal scheme is proposed in section II. The algorithm of Viterbi encoding scheme in presented in section III. Section IV the presents the simulation results, RTL views and discussion part. Comparative analysis of Synthesis report and timing parameters are listed in section V. 
\section[{II.}]{II.} 
\section[{Spatio Temporal Bus Encoding \& Decoding}]{Spatio Temporal Bus Encoding \& Decoding}\par
Spatio encoding \hyperref[b11]{[12]} is applicable for arbitrary bus encoding .This techniques are proposed for 8 bits, 16 bits or ' N' bits data. Spatio temporal bus encoding scheme is proposed for eliminates the crosstalk classes \hyperref[b10]{[11]} [13] for large energy consumption and delay of the buses \hyperref[b11]{[12]}. This scheme is also designed to have builtin error detection \hyperref[b9]{[10]} with very less circuit overhead. The architectures for the encoder and decoder circuit of the Spatio temporal encoding scheme are given in figure \hyperref[fig_1]{1}(a) and 1(b). The architecture of the Spatio encoder is proposed for scheme an 8 bits data bus. In the encoder which have data d t and previous encoded data E t-1 . There are two multiplexers \hyperref[b10]{[11]} which have 3 common inputs from data d t and two XOR gates. It's output is E t and E t+1 . The data sent on the bus at time instance t-1 is stored in a register of 9 bits. It is denoted by E t-1 . The present data is stored in register which are denoted by d t . First multiplexer (2 x 1) has two inputs which are common may be any one bit of data d t (1), d t (2) and d t (3). The selection line of this multiplexer is directly configured as XOR output \hyperref[b11]{[12]} of d t (  {\ref 2}) and E X-1 \hyperref[b1]{(2)}. The output of this multiplexer is common input \hyperref[b12]{[13]} [14] for E t (  {\ref 1}), E t (  {\ref 2}), E x (3), E x (4). Another multiplexer also has common inputs lines which are d t (5), d t (  {\ref 6}) and d t \hyperref[b6]{(7)} followed by XORed selection line of d t (  {\ref 6}) and E t-1 \hyperref[b7]{(8)}. The decoding method for the proposed scheme is similar \hyperref[b14]{[15]}. In decoding scheme \hyperref[b1]{[2]} [12] \hyperref[b14]{[15]} the original data d t is reconstructed from E t and E t+1 . Where E t+1 and E t are the input to the decoder and d t is obtained by the decoding algorithm. The first three bits of d t (1), d t (2) and d t (3) are common output of first multiplexer. This multiplexer accepts common input of E t (1), E t (  {\ref 2}) and E t (3). E t+1 (3) is the selection logic of this multiplexer. First bit of E t+1 (1) is directly configured with d t (4). Another multiplexer accepts common inputs of E t (  {\ref 7}), E t (  {\ref 8}) and E t \hyperref[b8]{(9)}. Selection logic of this multiplexer is E t+1 \hyperref[b8]{(9)}. The output of this multiplexer gives the values of d t (5), d t (6) and d t \hyperref[b6]{(7)}. d t (  {\ref 8}) is directly configured with E t+1 \hyperref[b6]{(7)}. For an example, consider an 8-bit data bus \hyperref[b1]{[2]} for which encoded data will be of 9-bit length. Let the data be already available on the bus (9 bit)  {\ref [} . Here transaction 0-1, 1-0 and 1-1 are represented by .\par
III. 
\section[{Viterbi Encoding \& Decoding}]{Viterbi Encoding \& Decoding}\par
Conventional codes are helping to analysis the Viterbi algorithm \hyperref[b2]{[3]}. Viterbi algorithm are supported by two steps, the initial step is to select the trellis from the bits that are achieved at the input at the receiver. A simple trellis \hyperref[b0]{[1]} show with 4 stage points for transmission, each state is represented with a dot and  The Encoded vector Hence the value of first encoded vector is 101. Similarly second bit form MSB is entered in shift register, second bit interval E 1 =1, E 2 =1, E 3 =0. Vector corresponding to second bit is Hence the value of second encoded vector is 101. In the same manner encoded vectors \hyperref[b0]{[1]} \hyperref[b15]{[16]} for other bit intervals can be found. The register will reset at seventh bit interval because maximum condition \hyperref[b15]{[16]} of reset is (L+K=  {\ref 4+3= 7)}. The output at each bit interval consists of V bits. Thus for each message there are (L+K) encoded vectors in the output code word. In the given table the coded output bit stream for all input data stream for encoder. Similarly, the encoding of 8 bit can understand. Considering and 8 bit input stream 10111010. Initially shift register contents are 000. First bit of MSB is entered in shift register then E 1 =1, E 2 =0, E 3 =0 the first encoded vector calculation Hence the value of first encoded vector is 101. Similarly second bit is entered from MSB, the contents of shift register will be E 1 =0, E 2 =1, E 3 =0, the conceded vector Hence the value of second encoded vector is 110. The register will reset at seventh bit interval because maximum condition of reset is (L+K= 8+3= 11). In the same manner encoded vectors for other bit intervals can be found and the encoded vectors are 11. Table \hyperref[tab_2]{2} lists the values of encoded vectors for 8 bits input data stream.  The Viterbi algorithm applies the maximumlikelihood principle \hyperref[b2]{[3]}. The most common metric used is the Hamming distance metric \hyperref[b0]{[1]}. This is just the dot product between the received codeword and the allowable codeword. These metrics are cumulative so that the path with the largest total metric is the final winner. The selection of survivor path is the main feature of the Viterbi algorithm and ensures that the algorithm terminates with the maximum likelihood path. The algorithm terminates when all of the nodes in the trellis have been labeled and their entering survivor paths are determined \hyperref[b15]{[16]}. IV.V = [V 1 V 2 V 3 ] in which the values of V 1 , V 2 and V 3 of the adders are V 1 = E 1 XOR E 2 , V 2 = E 2 XOR E 3 , V 3 = E 1 XOR E 3 .?? 1 =1 ? 0 = 1, ?? 2 = 0 ? 0 = 0, ?? 3 = 1 ? 0 = 1 ?? 1 = 1 ? 1 = 0, ?? 2 = 1 ? 0 = 1, ?? 3 = 1 ? 0 = 1 ?? 1 = 1 ? 0 = 1, ?? 2 = 0 ? 0 = 0, ?? 3 = 0 ? 1 = 1 ?? 1 = 0 ? 1 = 1, ?? 2 = 1 ? 0 = 1, ?? 3 = 0 ? 0 = 0 Global Journal of 
\section[{Simulation Result \& Discussion}]{Simulation Result \& Discussion}\par
The snapshot shown in figure  {\ref 4}   \hyperref[tab_3]{3} explains the role of pins and their functions.    
\section[{Comparative Analysis}]{Comparative Analysis}\par
Comparative analysis of Spatio and Viterbi encoding and decoding Schemes can be done by the timing parameters and device utilization summary extracted from Xilinx. Device utilization summary is the report of used device hardware in the implementation of the chip such as RAM, ROM, slices, flip flops etc. Synthesis report shows the complete details of device utilization as total memory utilization. If synthesis report does not have the optimized hardware, further chip development can be done in the Xilinx ISE design software.\par
The device targeted for synthesis on SPARTEN-3E FPGA .Timing parameters are synchronized with the clock signal. Timing details provides the information of net delay, minimum period, minimum input arrival time before clock and maximum output required time after clock. Table \hyperref[tab_4]{4} compares the hardware utilization for Spatio and Viterbi Encoders. Table \hyperref[tab_5]{5} compares the hardware utilization for Spatio and Viterbi decoders. Table \hyperref[tab_6]{6} shows the timing parameter of Spatio and Viterbi Encoders and decoders.   The memory utilization graph is shown in figure \hyperref[fig_11]{8}   
\section[{Conclusion}]{Conclusion}\par
The hardware chip for Viterbi encoder and decoder, Spatio encoder and decoder is implemented in Xilinx 14.2 and functionally checked in Modelsim 10.1b software. A comparative analysis is done with respect to hardware and timing parameters. In the chip implementation, it is analyzed that Spatio encoding and decoding is having less delay in comparison to Viterbi encoding and decoding. Memory utilization is less which is 1.75 \% for Spatio encoder 4.33 \% for Spatio decoder in comparison to Viterbi encoder and decoder. But there is a reduction of 48 \% in combinational path delay in Spatio encoder and 42 \% in Spatio decoder in comparison to Viterbi encoder and decoder. Hence Spatio encoding and decoding scheme is faster in comparison to Viterbi encoding and decoding.  
\section[{Global}]{Global}\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_1}Figure 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-3.png}
\caption{\label{fig_2}A}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-4.png}
\caption{\label{fig_3}Figure 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-5.png}
\caption{\label{fig_4}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-6.png}
\caption{\label{fig_6}Figure 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-7.png}
\caption{\label{fig_7}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{42526}\includegraphics[]{image-8.png}
\caption{\label{fig_8}Figure 4 2 GlobalFigure 5 2 GlobalFigure 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-9.png}
\caption{\label{fig_9}Figure 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-10.png}
\caption{\label{fig_10}Selected}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{8}\includegraphics[]{image-11.png}
\caption{\label{fig_11}Figure 8 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-12.png}
\caption{\label{fig_12}}\end{figure}
     \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{P{0.13240384615384615\textwidth}P{0.6391346153846154\textwidth}P{0.07846153846153846\textwidth}}
Input data stream\tabcellsep Coded output bit stream\tabcellsep \\
0000\tabcellsep 000 000 000 000 000 000\tabcellsep 000\\
0001\tabcellsep 000 000 000 101 110 011\tabcellsep 000\\
0010\tabcellsep 000 000 101 110 011 000\tabcellsep 000\\
0011\tabcellsep 000 000 101 011 101 011\tabcellsep 000\\
0100\tabcellsep 000 101 110 011 000 000\tabcellsep 000\\
0101\tabcellsep 000 101 110 110 110 011\tabcellsep 000\\
0110\tabcellsep 000 101 011 101 011 000\tabcellsep 000\\
0111\tabcellsep 000 101 011 000 101 011\tabcellsep 000\\
1000\tabcellsep 101 110 011 000 000 000\tabcellsep 000\\
1001\tabcellsep 101 110 011 101 110 011\tabcellsep 000\\
1010\tabcellsep 101 110 110 110 011 000\tabcellsep 000\\
1011\tabcellsep 101 110 110 011 101 011\tabcellsep 000\\
1100\tabcellsep 101 011 101 011 000 000\tabcellsep 000\\
1101\tabcellsep 101 011 101 110 110 011\tabcellsep 000\\
1110\tabcellsep 101 011 000 101 011 000\tabcellsep 000\\
1111\tabcellsep 101 011 000 000 101 011\tabcellsep 000\end{longtable} \par
 
\caption{\label{tab_1}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.36124999999999996\textwidth}P{0.48874999999999996\textwidth}}
Input data stream\tabcellsep Coded output bit stream\end{longtable} \par
 
\caption{\label{tab_2}Table 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3} \par 
\begin{longtable}{P{0.1701800847457627\textwidth}P{0.6798199152542374\textwidth}}
Year\tabcellsep \\
Pins\tabcellsep Functional Description\\
clk\tabcellsep Signal produce to Clock signal ( 1 bit of std\textunderscore logic)\\
Reset\tabcellsep used for synchronization of the components by using clk ( 1 bit of std\textunderscore logic)\\
Tx\tabcellsep 9 bit encoded data by Spatio encoder at time t\\
Tx\textunderscore Minus\tabcellsep 9 bit encoded data by Spatio encoder at time t-1\\
Tx\textunderscore plus\tabcellsep 9 bit encoded data by Spatio encoder at time t+1\\
dt\tabcellsep Input data of Spatio Encoder and output of Spatio Decoder (8 bits of std\textunderscore logic\textunderscore vector)\\
Data\textunderscore stream\tabcellsep Input data of 8 bit for Viterbi Encoder (8 bits of std\textunderscore logic\textunderscore vector)\\
Encoded\textunderscore vector\textunderscore data\tabcellsep Array of Encoded data (0 to 10) for 8 bit data\textunderscore stream(8 bits of std\textunderscore logic\textunderscore vector)\\
Decoded\textunderscore data\textunderscore stream\tabcellsep Decoded output of Viterbi decoder (8 bits of std\textunderscore logic\textunderscore vector)\end{longtable} \par
 
\caption{\label{tab_3}Table 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4} \par 
\begin{longtable}{P{0.3298951048951049\textwidth}P{0.27937062937062934\textwidth}P{0.050524475524475525\textwidth}P{0.05944055944055944\textwidth}P{0.020804195804195805\textwidth}P{0.050524475524475525\textwidth}P{0.05944055944055944\textwidth}}
Device part\tabcellsep \multicolumn{6}{l}{Viterbi Encoder Used Available Utilization Used Available Utilization Spatio Encoder}\\
Number of Slices\tabcellsep 60\tabcellsep 2448\tabcellsep 2\%\tabcellsep 1\tabcellsep 2448\tabcellsep 0 \%\\
Number of Slice Flip Flops\tabcellsep 23\tabcellsep 4896\tabcellsep 0 \%\tabcellsep 2\tabcellsep 4896\tabcellsep 0 \%\\
Number of 4 input LUTs\tabcellsep 105\tabcellsep 4896\tabcellsep 2 \%\tabcellsep 50\tabcellsep 4896\tabcellsep 1\%\\
Number of bonded IOBs\tabcellsep 43\tabcellsep 158\tabcellsep 27 \%\tabcellsep 46\tabcellsep 158\tabcellsep 29 \%\\
Number of GCLKs\tabcellsep 1\tabcellsep 24\tabcellsep 4 \%\tabcellsep 1\tabcellsep 24\tabcellsep 4 \%\end{longtable} \par
 
\caption{\label{tab_4}Table 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5} \par 
\begin{longtable}{P{0.3310526315789474\textwidth}P{0.2743859649122807\textwidth}P{0.05070175438596491\textwidth}P{0.05964912280701754\textwidth}P{0.023859649122807018\textwidth}P{0.05070175438596491\textwidth}P{0.05964912280701754\textwidth}}
Device part\tabcellsep \multicolumn{6}{l}{Viterbi Decoder Used Available Utilization Used Available Utilization Spatio Decoder}\\
Number of Slices\tabcellsep 34\tabcellsep 2448\tabcellsep 1\%\tabcellsep 26\tabcellsep 2448\tabcellsep 1\%\\
Number of Slice Flip Flops\tabcellsep 43\tabcellsep 4896\tabcellsep 0 \%\tabcellsep 33\tabcellsep 4896\tabcellsep 0 \%\\
Number of 4 input LUTs\tabcellsep 6\tabcellsep 4896\tabcellsep 0 \%\tabcellsep 4\tabcellsep 4896\tabcellsep 0 \%\\
Number of bonded IOBs\tabcellsep 18\tabcellsep 158\tabcellsep 11 \%\tabcellsep 16\tabcellsep 258\tabcellsep 10 \%\\
Number of GCLKs\tabcellsep 1\tabcellsep 24\tabcellsep 4 \%\tabcellsep 1\tabcellsep 24\tabcellsep 4 \%\end{longtable} \par
 
\caption{\label{tab_5}Table 5 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6} \par 
\begin{longtable}{P{0.2954035874439462\textwidth}P{0.024775784753363228\textwidth}P{0.12387892376681614\textwidth}P{0.2077354260089686\textwidth}P{0.09910313901345291\textwidth}P{0.09910313901345291\textwidth}}
\multicolumn{2}{l}{Parameter}\tabcellsep Viterbi Encoder\tabcellsep \multicolumn{3}{l}{Utilization Viterbi Decoder Spatio Encoder Spatio Decoder}\\
\multicolumn{2}{l}{Minimum Period}\tabcellsep 3.047ns\tabcellsep 2.058 ns\tabcellsep 1.578 ns\tabcellsep 1.567 ns\\
\multicolumn{2}{l}{Minimum input arrival time before clock}\tabcellsep 8.515ns\tabcellsep 4.053 ns\tabcellsep 2.056 ns\tabcellsep 2.023 ns\\
\multicolumn{2}{l}{Maximum output required time after clock}\tabcellsep 4.179ns\tabcellsep 4.179 ns\tabcellsep 3.0567 ns\tabcellsep 3.067 ns\\
Maximum path delay\tabcellsep combinational\tabcellsep 12.014 ns\tabcellsep 10.057 ns\tabcellsep 6.232ns\tabcellsep 5.797 ns\\
\multicolumn{2}{l}{Maximum Frequency}\tabcellsep 325.165 MHz\tabcellsep 325.53 MHz\tabcellsep 325 .27 MHz\tabcellsep 325 .10 MHz\\
\multicolumn{2}{l}{Memory Utilization}\tabcellsep 116408 kB\tabcellsep 115384 kB\tabcellsep 114360 kB\tabcellsep 110380 kB\end{longtable} \par
 
\caption{\label{tab_6}Table 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{} \par 
\begin{longtable}{P{0.85\textwidth}}
VI.\end{longtable} \par
 
\caption{\label{tab_7}}\end{figure}
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