@incollection{,
	
					
					
					A477895F0537794CC978F0B70A347601
				,
	author={{KartikaVyas} and {NaveenChoudhary} and {DharmSingh} and {Maharana Pratap Agriculture University}},
	journal={{Global Journal of Computer Science and Technology}},
	journal={{GJCST}}0975-41720975-435010.34257/gjcst,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}1314712
}

@incollection{b0,
	
	
		,
	title={{GARNET: A detailed on-chip network model inside a full system simulator}}
		,
	author={{
			NAgrawal
		} and {
			TKrishna
		} and {
			LSPeh
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			NKJha
		}}
		
		
		
	
	
		,
	booktitle={{IEEE International Symposium on Performance Analysis of Systems and Software}}
				
			,
	year={2009}
			
		
	

}

@incollection{b1,
	
	
		,
	title={{Network-on-chip design and synthesis outlook}}
		,
	author={{
			DAtienza
		} and {
			FAngiolini
		} and {
			SMurali
		} and {
			APullini
		} and {
			LBenini
		} and {
			GDMicheli
		}}
		
		
		
		
		
	
	
		,
	journal={{In Integration-The VLSI journal}}
		
			41
			3
			
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	year={2008}
		
	

}

@incollection{b2,
	
	
		,
	title={{Networks on chips: A new SoC paradigm}}
		,
	author={{
			LBenini
		} and {
			GDMicheli
		}}
		
	
	
		,
	booktitle={{IEEE Computer}}
				
			,
	year={2002}
			35
			
		
	

}

@incollection{b3,
	
	
		,
	title={{Irregular NoC simulation framework: IrNIRGAM}}
		,
	author={{
			NChoudhary
		} and {
			MSGaur
		} and {
			VLaxmi
		}}
		
		
	
	
		,
	booktitle={{International Conference on Emerging Trends in Networks and Computer Communications (ETNCC)}}
				
			,
	year={2011}
			
		
	

}

@book{b4,
	
	
		,
	title={{Principles and practices of interconnection networks. Publication}}
		,
	author={{
			WJDally
		} and {
			BTowles
		}}
		
		
			,
	year={2004}
			,
	publisher={Elsevier/Morgan Kaufmann}
			,
	address={Amsterdam, London}
		
	

}

@incollection{b5,
	
	
		,
	title={{Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation}}
		,
	author={{
			BSFeero
		} and {
			PPPande
		}}
		
	
	
		,
	booktitle={{IEEE Transactions on Computers}}
				
			,
	year={2009}
			58
			
		
	

}

@incollection{b6,
	
	
		,
	title={{The turn model for adaptive routing}}
		,
	author={{
			CJGlass
		} and {
			LMNi
		}}
		
	
	
		,
	booktitle={{Proceedings of 19 th Annual International Symposium on Computer Architecture}}
				19 th Annual International Symposium on Computer Architecture
		
			,
	year={1992}
			
		
	

}

@incollection{b7,
	
	
		,
	title={{Replacing global wires with an on-chip network: a power analysis}}
		,
	author={{
			SHeo
		} and {
			KAsanovic
		}}
		
	
	
		,
	booktitle={{Proceedings of the International Symposium on Low power electronics and design}}
				the International Symposium on Low power electronics and design
		
			,
	year={2005}
			
		
	

}

@incollection{b8,
	
	
		,
	title={{Gpnocsim -A General Purpose Simulator for Network-On-Chip}}
		,
	author={{
			HHossain
		} and {
			MAhmed
		} and {
			AAl-Nayeem
		} and {
			TZIslam
		} and {
			MMAkbar
		}}
		
		
		
		
	
	
		,
	booktitle={{International Conference on Information and Communication Technology}}
				
			,
	year={2007}
			
		
	

}

@book{b9,
	
	
		,
	title={{Design methodologies for application specific networks-onchip}}
		,
	author={{
			JHu
		}}
		
			,
	year={2005}
		
		
			Carnegie Mellon University
		
	
	,
	note={PhD thesis}

}

@book{b10,
	
	
		,
	title={{NIRGAM: a simulator for noc interconnect routing application modeling}}
		,
	author={{
			LJain
		} and {
			BMAl-Hashimi
		} and {
			MSGaur
		} and {
			VLaxmi
		} and {
			ANarayanan
		}}
		
		
		
		
		
			,
	year={2007}
			2007
		
	

}

@incollection{b11,
	
	
		,
	title={{}}
		,
	author={{
			NJiang
		}}
		
	
	
		,
	journal={{BookSim Interconnection Network Simulator.Online}}
		
	

}

@book{b12,
	
	
		,
	title={{NoCsim: a versatile network on chip simulator}}
		,
	author={{
			MJones
		}}
		
		
			,
	year={2005}
		
	

}

@incollection{b13,
	
	
		,
	title={{NNSE: Nostrum Network-on-Chip Simulation Environment}}
		,
	author={{
			ZLu
		} and {
			RThid
		} and {
			MMillberg
		} and {
			ENilsson
		} and {
			AJantsch
		}}
		
		
		
		
		
	
	
		,
	booktitle={{Swedish System-on-Chip Conference}}
				Stockholm, Sweden
		
			,
	year={2005}
		
	
	,
	note={cycle-level NoC simulator}

}

@incollection{b14,
	
	
		,
	title={{}}
		,
	author={{
			RPalesi
		}}
		
	
	
		,
	journal={{Noxim: the NoC Simulator. Online}}
		
	

}

@book{b15,
	
	
		,
	title={{Ocin tsim-DVFS aware simulator for NoCs}}
		,
	author={{
			SPrabhu
		} and {
			BGrot
		} and {
			PVGratz
		} and {
			JHu
		}}
		
		
		
		
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	year={2009}
		
	

}

@incollection{b16,
	
	
		,
	title={{SICOSYS: an integrated framework for studying interconnection network performance in multiprocessor systems}}
		,
	author={{
			VPuente
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			JAGregorio
		} and {
			RBeivide
		}}
		
		
	
	
		,
	booktitle={{Euromicro Workshop on Parallel, Distributed and Network based Processing}}
				
			,
	year={2002}
			
		
	

}

@incollection{b17,
	
	
		,
	title={{Autonet: A highspeed self-configuring local area network using point-to-point links}}
		,
	author={{
			MDSchroeder
		}}
	
	
		,
	journal={{In Journal on Selected Areas in Communications}}
		
			9
			
			,
	year={1991}
		
	

}

@incollection{b18,
	
	
		,
	title={{High-performance routing in networks of workstations with irregular topology}}
		,
	author={{
			FSilla
		} and {
			JDuato
		}}
		
	
	
		,
	booktitle={{IEEE Transactions on Parallel and Distributed Systems}}
				
			,
	year={2000}
			11
			
		
	

}

@book{b19,
	
	
		,
	title={{Darsim: A parallel}}
		,
	author={{
			LMieszko
		} and {
			SKSup
		} and {
			CMHyon
		} and {
			RPengju
		} and {
			OKhan
		} and {
			SDevadas
		}}
		
		
		
		
		
		
			,
	year={2010}
		
	

}