@incollection{,
	
					
					
					AD5258E0B913E07E8CF21589D768AE70
				,
	author={{RajeshwariSoma} and {ZulekhaTabassum} and {S.Prathap} and {JNTUH}},
	journal={{Global Journal of Computer Science and Technology}},
	journal={{GJCST}}0975-41720975-435010.34257/gjcst,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}13102128
}

@book{b0,
	
	
		,
	author={{
			NAhmed
		} and {
			MTehranipoor
		}}
		
		,
	title={{Nanometer Technology Designs: High Quality Delay Tests}}
				New York
		
			,
	publisher={Springer}
			,
	year={2007}
		
	

}

@incollection{b1,
	
	
		,
	title={{A small-delay defect detection technique for dependable LSIs}}
		,
	author={{
			KNoguchi
		} and {
			KNose
		} and {
			TOno
		} and {
			MMizuno
		}}
		
		
		
	
	
		,
	booktitle={{Proc. IEEE Symp. VLSI Circuits}}
				IEEE Symp. VLSI Circuits
		
			,
	year={2008}
			
		
	

}

@incollection{b2,
	
	
		,
	title={{Design for testability: Using scan path techniques for pathdelay test and measurement}}
		,
	author={{
			BIDervisoglu
		} and {
			GEStong
		}}
		
	
	
		,
	booktitle={{Proc. IEEE Int. Test Conf. (ITC)}}
				IEEE Int. Test Conf. (ITC)
		
			,
	year={1991}
			
		
	

}

@incollection{b3,
	
	
		,
	title={{An area reduction technique of self-testing FFs for small delay defects detection}}
		,
	author={{
			KNoguchi
		} and {
			KNose
		} and {
			TOno
		} and {
			MMizuno
		}}
		
		
		
	
	
		,
	journal={{The Inst. Electron., Inf. Commun. Eng}}
		
			,
	publisher={IEICE}
		
	
	,
	note={Tech. Rep. DC2009-16}

}

@book{b4,
	
	
		,
	title={{Delay Fault Testing for VLSI Circuits}}
		,
	author={{
			AKrstic
		} and {
			K.-TChen
		}}
		
		
			,
	year={1998}
			,
	publisher={Kluwer}
			,
	address={Norwell, MA}
		
	

}

@incollection{b5,
	
	
		,
	title={{Enhancing test efficiency for delay fault testing using multiple clocked schemes}}
		,
	author={{
			J.-JLiou
		} and {
			L.-CWang
		} and {
			K.-TCheng
		}}
		
		
	
	
		,
	booktitle={{Proc. Des. Autom. Conf. (DAC)}}
				Des. Autom. Conf. (DAC)
		
			,
	year={2002}
			
		
	

}

@incollection{b6,
	
	
		,
	title={{Evaluating the effectiveness of detecting delay defects in the slack interval: A simulation study}}
		,
	author={{
			HYan
		} and {
			ADSingh
		}}
		
	
	
		,
	booktitle={{Proc. IEEE Int. Test Conf. (ITC)}}
				IEEE Int. Test Conf. (ITC)
		
			,
	year={2004}
			
		
	

}

@incollection{b7,
	
	
		,
	title={{Failing frequency signature analysis}}
		,
	author={{
			JLee
		} and {
			EJMccluskey
		}}
		
	
	
		,
	booktitle={{Proc. Int. Test Conf. (ITC)}}
				Int. Test Conf. (ITC)
		
			,
	year={2008}
			
		
	

}

@incollection{b8,
	
	
		,
	title={{On-chip programmable capture for accurate path delay test and characterization}}
		,
	author={{
			RTayade
		} and {
			JAAbraham
		}}
		
	
	
		,
	booktitle={{Proc. IEEE Int. Test Conf. (ITC)}}
				IEEE Int. Test Conf. (ITC)
		
			,
	year={2008}
			
		
	

}

@incollection{b9,
	
	
		,
	title={{Logic design for on-chip test clock generationimplementation details and impact on delay test quality}}
		,
	author={{
			MBeck
		} and {
			OBarondeau
		} and {
			XLin
		} and {
			RPress
		}}
		
		
		
	
	
		,
	booktitle={{Proc. IEEE Des., Autom. Test Eur. Conf. Exhib. (DATE)}}
				IEEE Des., Autom. Test Eur. Conf. Exhib. (DATE)
		
			,
	year={2005}
			
		
	

}

@incollection{b10,
	
	
		,
	title={{A 1-to-2GHz 4-phaseon-chip clock generator with timing margin test capability}}
		,
	author={{
			SKaeriyama
		} and {
			MKajita
		} and {
			MMizuno
		}}
		
		
	
	
		,
	booktitle={{Dig. Tech. Paper Int. Solid-State Circuits Conf. (ISSCC)}}
				
			,
	year={2007}
			
		
	

}

@book{b11,
	
	
		,
	title={{}}
		,
	author={{
			T.-YLi
		} and {
			S.-YHuang
		} and {
			H.-JHsu
		} and {
			C.-WTzeng
		} and {
			C.-T
		}}
		
		
		
		
		
	

}

@incollection{b12,
	
	
		,
	title={{A novel faster-thanat speed transition-delay test method considering IR-drop effects}}
		,
	author={{
			J.-JHuang
		} and {
			H.-PLiou
		} and {
			P.-CMa
		} and {
			J.-CHuang
		} and {
			C.-WBor
		} and {
			Wu
		}}
		
		
		
		
		
	
	
		,
	booktitle={{Proc. IEEE Int. Symp. Defect Fault Toler. VLSI Syst.(DFT), 2010, 13. N. Ahmed and M. Tehranipoor}}
				IEEE Int. Symp. Defect Fault Toler. VLSI Syst.(DFT), 2010, 13. N. Ahmed and M. Tehranipoor
		
			,
	year={Oct. 2009}
			28
			
		
	
	,
	note={Af test: Adaptive-frequency scan test methodology for small-delay defects}

}

@incollection{b13,
	
	
		,
	title={{Test-pattern grading and pattern selection for small delay defects}}
		,
	author={{
			MYilmaz
		} and {
			KChakrabarty
		} and {
			MTehranipoor
		}}
		
		
	
	
		,
	booktitle={{Proc. IEEE VLSI Test Symp. (VTS)}}
				IEEE VLSI Test Symp. (VTS)
		
			,
	year={2008}
			
		
	

}

@incollection{b14,
	
	
		,
	title={{On hazard-free patterns for finedelay fault testing}}
		,
	author={{
			BKruseman
		} and {
			AKMajhi
		} and {
			GGronthoud
		} and {
			SEichenberger
		}}
		
		
		
	
	
		,
	booktitle={{Proc. Int. Test Conf.(ITC)}}
				Int. Test Conf.(ITC)
		
			,
	year={2004}
			
		
	

}

@incollection{b15,
	
	
		,
	title={{Bounding circuit delay by testing a very small subset of paths}}
		,
	author={{
			MSharma
		} and {
			JHPatel
		}}
		
	
	
		,
	booktitle={{Proc. IEEE VLSI Test Symp}}
				IEEE VLSI Test Symp
		
			,
	year={2000}
			
		
	

}