Design and FPGA Implementation of High Speed DWT-IDWT Architecture with Pipelined SPIHT Architecture for Image Compression
Keywords:
SPIHT, DWT, pipelined architecture, FPGA, High speed, image compress ion
Abstract
Image compression demands high speed architectures for transformation and encoding process Medical image compression demands lossless compression schemes and faster architectures A trade-off between speed and area decides the complexity of image compression algorithms In this work a high speed DWT architecture and pipelined SPIHT architecture is designed modeled and implemented on FPGA platform DWT computation is performed using matrix multiplication operation and is implemented on Virtex-5 FPGA that consumes less than 1 of the hardware resource The SPIHT algorithm that is performed using pipelined architecture and hence achieves higher throughput and latency The SPIHT algorithm operates at a frequency of 260 MHz and occupies area less than 15 of the resources The architecture designed is suitable for high speed image compression applications
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Published
2014-01-15
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Copyright (c) 2014 Authors and Global Journals Private Limited
This work is licensed under a Creative Commons Attribution 4.0 International License.