@incollection{,
	
					
					
					379876626ECD3EFED8ADB4617C1F1D35
				,
	author={{Dr. M.Nagabushanam} and {S.Ramachandran} and {Anna University, Coimbatore, India.}},
	journal={{Global Journal of Computer Science and Technology}},
	journal={{GJCST}}0975-41720975-435010.34257/gjcst,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}12112329
}

@incollection{b0,
	
	
		,
	title={{Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters}}
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	author={{
			Tze-YunSung
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			Hsi-Chin Hsin Yaw-Shih
		} and {
			Chun-WangShieh
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			Yu
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	booktitle={{Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies}}
				
			,
	year={December 2006}
		
	

}

@incollection{b1,
	
	
		,
	title={{VLSI Implementation of Discrete Wavelet Transform (DWT) for Image Compression}}
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			ALAbdullah
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			MdMuhit
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			MasuriIslam
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			Othman
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	booktitle={{2nd International Conference on Autonomous Robots and Agents}}
				
			,
	year={December 2004}
			
		
	

}

@incollection{b2,
	
	
		,
	title={{An efficient hardware implementation of DWT and IDWT}}
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	author={{
			ASMotra
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			PKBora
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			IChakrabarti
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	booktitle={{Conference on Convergent Technologies for Asia-Pacific Region}}
				
			,
	year={October 2003}
			
		
	

}

@incollection{b3,
	
	
		,
	title={{Design of highly efficient VLSI architectures for 2-D DWT and 2-D IDWT}}
		,
	author={{
			Yun-NanChang
		} and {
			Yan-ShengLi
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	journal={{IEEE Workshop on Signal Processing Systems}}
		
			
			,
	year={September 2001}
		
	

}

@incollection{b4,
	
	
		,
	title={{VLSI architectures for discrete wavelet transforms}}
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	author={{
			KKeshab
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			TakaoParhi
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			Nishitani
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	booktitle={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}
				
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	year={June 1993}
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}

@book{b5,
	
	
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	title={{JPEG 2000 -Image compression, fundamentals, standards and practice}}
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	author={{
			DavidSTaubman
		} and {
			MichaelWMarcellin
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			,
	year={2002}
			,
	publisher={Kluwer academic publishers}
		
	
	,
	note={Second Edition}

}

@incollection{b6,
	
	
		,
	title={{Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA}}
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	author={{
			SimoneBorgio
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	booktitle={{Embedded Computer Systems: Architectures, Modeling and Simulation}}
				
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	year={2006. 2006. July 2006}
			
		
	

}

@book{b7,
	
	
		,
	title={{Designing Low-Power Signal Processing Systems}}
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	author={{
			MelTsai
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			Bdti
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}

@incollection{b8,
	
	
		,
	title={{Low-power and high-performance 2-D DWT and IDWT architectures based on 4-tap Daubechies filters}}
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	author={{
			Tze-Yun
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		,
	booktitle={{Proceedings of the 7th WSEAS International Conference on Multimedia Systems and Signal Processing}}
				the 7th WSEAS International Conference on Multimedia Systems and Signal ProcessingHangzhou, China
		
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	year={2007}
			
		
	

}

@incollection{b9,
	
	
		,
	title={{Low power domain-specific reconfigurable array for discrete wavelet transforms targeting multimedia applications}}
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	author={{
			SBaloch
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			AStoica
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	booktitle={{International Conference on Field Programmable Logic and Applications}}
				
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	year={2005}
			
		
	
	,
	note={International Conference on Field Programmable Logic and Applications}

}

@incollection{b10,
	
	
		,
	title={{A Low-Power Multiplier with the Spurious Power Suppression Technique}}
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	author={{
			HungKuan
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			Yuan-SunChen
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			Chu
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	journal={{IEEE Trans. On Very Large Scale Integration (VLSI) Systems}}
		
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	year={July 2007}
		
	

}

@incollection{b11,
	
	
		,
	title={{A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform}}
		,
	author={{
			KishoreAndra
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			TinkuacharyaChaitalichakrabarti
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	journal={{IEEE Transaction on signal processing}}
		
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	year={April 2002}
		
	

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@incollection{b12,
	
	
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	title={{A novel architecture for lifting-based discrete wavelet transform for JPEG2000 standard suitable for VLSI Implementation" VLSI Design}}
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	author={{
			SMovva
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			SSrinivasan
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	booktitle={{Proceedings. 16 th International Conference On 4-8}}
				16 th International Conference On 4-8Page(s
		
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	year={2003. Jan. 2003}
			
		
	

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@incollection{b13,
	
	
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	title={{A Pipelined Multiply-Accumulate Unit Design for Energy Recovery DSP Systems}}
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	author={{
			CDusansuvakovic
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			SalamaAndre
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	booktitle={{IEEE International Symposium on Circuits and Systems}}
				
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	year={May 28-31, 2000}
		
	

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@incollection{b14,
	
	
		,
	title={{A Simple High-Speed Multiplier Design}}
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	author={{
			Jung-YupKang
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			Jean-LucGaudiot
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	year={October 2006}
		
	

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@incollection{b15,
	
	
		,
	title={{Highperformance Low-power Left-to-Right Array Multiplier Design}}
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	author={{
			ZhijunHuang
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			MilosDErcegovac
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	journal={{IEEE Transactions on computers}}
		
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	year={Mar 2005}
		
	

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@incollection{b16,
	
	
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	title={{A Suggestion for a Fast Multiplier}}
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	author={{
			CSWallace
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	journal={{IEEE Trans. computers}}
		
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	year={1964}
		
	

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@incollection{b17,
	
	
		,
	title={{Comparison of high-performance VLSI adders in the energy-delay space}}
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	author={{
			GVojin
		} and {
			BartROklobzija
		} and {
			Zaydel
		} and {
			QHoang
		} and {
			SanuDao
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			RamMathew
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			Krishnamurthy
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	journal={{IEEE Trans. VLSI Systems}}
		
			13
			6
			
			,
	year={June 2005}
		
	

}

@incollection{b18,
	
	
		,
	title={{A Fast and Well structured Multiplier}}
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	author={{
			J-YKang
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			J-LGaudiot
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	booktitle={{EUROMICRO Symp. Digital System Design}}
				
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	year={Aug 2004}
			
		
	

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@incollection{b19,
	
	
		,
	title={{ModifiedVLSI implementation of DA-DWT for image compression}}
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	author={{
			MNagabushanam
		} and {
			Cyril Prasanna Raj
		} and {
			SRamachandran
		}}
		
		
	
	
		,
	journal={{International Journal of Signal and Imaging Systems Engineering}}
		
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}

@incollection{b20,
	
	
		,
	title={{Design and implementation of parallel and pipelined Distributive arithmetic based discrete wavelet transform IP core}}
		,
	author={{
			MNagabushanam
		} and {
			Cyril Prasanna Raj
		} and {
			SRamachandran
		}}
		
		
	
	
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	journal={{EJSR International Journal}}
		
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	year={2009}
		
	

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@incollection{b21,
	
	
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	title={{Design and FPGA implementation of Modified Distributive arithmetic based DWT-IDWT processor for image compression}}
		,
	author={{
			MNagabushanam
		} and {
			Cyril Prasanna Raj
		} and {
			SRamachandran
		}}
		
		
	
	
		,
	booktitle={{International Conference on Communication and Signal Processing}}
				February, NIT, Calicut, India
		
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	year={2011}
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@incollection{b22,
	
	
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	title={{BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture}}
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	author={{
			MMottaghi-Dastjerdi
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			AAfzali-Kusha
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			MPedram
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	booktitle={{IEEE Transactions on Very large Scale Integration (VLSI)systems}}
				
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	year={feb 2009}
			17
		
	

}