Abstract

Demand for high speed and low power architecture for DWT computation have led to design of novel algorithms and architecture. In this paper we design, model and implement a hardware efficient, high speed and power efficient DWT architecture based on modified lifting scheme algorithm. The design is interfaced with SIPO and PISO to reduce the number of I/O lines on the FPGA. The design is implemented on Spartan III device and is compared with lifting scheme logic. The proposed design operates at frequency of 280 MHz and consumes power less than 42 mW. The presynthesis and post-synthesis results are verified and suitable test vectors are used in verifying the functionality of the design. The design is suitable for real time data processing.

How to Cite
CHANDRA SEKHAR,DR. S.NARAYANA REDDY, Prof.C.. Performance Analysis of Modified Lifting Based DWT Architecture and FPGA Implementation for Speed and Power. Global Journal of Computer Science and Technology, [S.l.], aug. 2012. ISSN 0975-4172. Available at: <https://computerresearch.org/index.php/computer/article/view/591>. Date accessed: 27 jan. 2021.