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\title{Optimal High Performance Self Cascode CMOS Current Mirror}
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\begin{document}

             \author[1]{Vivek  pant}

             \affil[1]{  Kurukshetra university}

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\date{\small \em Received: 10 July 2011 Accepted: 8 August 2011 Published: 19 August 2011}

\maketitle


\begin{abstract}
        


In this paper the current mirror presented, having low voltage and mixed mode structure has been proposed. The performance of self cascade MOSFET current mirror is optimized with high output impedance and can operate at 1 V or below. Simulation results conform to Analog Mentor tools having Design Architect for schematics and Eldonet for SPICE simulation, with input reference current of 20 ?A. This review paper presents a comparative performance study of self cascode current mirror with other current mirrors.

\end{abstract}


\keywords{current mirrors, cascode current mirror, low voltage analog circuit.}

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\let\tabcellsep& 	 	 		 
\section[{INTRODUCTION}]{INTRODUCTION}\par
o meet the needs of present era of low power portable electronic equipment, many low voltage design techniques have been developed. This led to the analog designers to look for innovative design techniques like Self cascode CMOS Current Mirror \hyperref[b0]{[1]}\hyperref[b1]{[2]}\hyperref[b2]{[3]}\hyperref[b3]{[4]}\hyperref[b4]{[5]}. In this paper, we have investigated the merits and demerits of various current mirror configurations. For this we designed the basic current mirror first then improved our results by using various configurations like cascode current mirror, Wilson current mirror and finally the current mirror based on self cascode CMOS and analyzed its results through the SPICE simulations for 0.35 micron CMOS technology. 2  (1) 
\section[{II.}]{II.} 
\section[{BASIC MOSFET CURRENT MIRROR}]{BASIC MOSFET CURRENT MIRROR}I out = ½ ? n C ox (W/L) 2 (V gs -V th )I ref = ½ ? n C ox (W/L) 1 (V gs -V th ) 2 (2)\par
When eq. 1 is divided by eq. 2, we haveI out = I ref (W/L) 2 / (W/L) 1\par
Limitations 1. As we can see from the basic current mirror circuit current gain is poor and the output current is having the channel length modulation effects. This is verified in eq. 3I out = I ref (W/L) 2 (1+?V ds2 ) (3) (W/L) 1 (1+ ?V ds1 )\par
Here V ds1 ? V ds2 . 2. Output resistance is finite and small value.   
\section[{CASCODE CURRENT MIRROR}]{CASCODE CURRENT MIRROR}\par
The idea of cascode structure is employed to increase the output resistance (Fig. \hyperref[fig_3]{3}) and the implementation requires NMOS technology. It is used to T remove the drawback of channel length modulation in basic current mirror. In the simulation results of basic current mirror the channel length modulation effect was not considered. In practice, this effect results in significant error in copying currents. The circuit features a wide output voltage and requires an input voltage of approximately one diode drop plus a saturation voltage. By maintaining the input transistors in saturation, the output current will track the input current, regardless of increases in ambient temperature \hyperref[b5]{[6,}\hyperref[b6]{7,}\hyperref[b7]{8]}.\par
The basic current mirror can also be implemented using MOSFET transistors (Fig: \hyperref[fig_0]{1}). Transistor M1 is operating in the saturation or active mode, and so is M2. In this setup, the output current IOUT is directly related to IREF, as discussed next.   
\section[{WILSON CURRENT MIRROR}]{WILSON CURRENT MIRROR}\par
A Wilson current mirror or Wilson current source is a circuit configuration designed to provide a constant current (Fig: \hyperref[fig_4]{5}). This circuit has the advantage of virtually eliminating the current mis-match of the conventional current mirror thereby ensuring that the output current I out is almost equal to the reference or input current I Ref thus eliminating the drawbacks of cascode structure. Simulation results for Iout vs V ds curve for Wilson Current Mirror are shown in fig 6  {\ref .} Advantages:\par
1. Curve is much flatter than basic and cascode current mirrors. 2. Output resistance becomes even much higher than cascode current mirror. This is caused by two positive feedback effects.\par
Disadvantages:\par
1. Current becomes constant for quite large value of Vds e.g. in this case minimum Vds is 1.22V.  
\section[{LOW VOLTAGE SELF CASCODE CURRENT MIRROR}]{LOW VOLTAGE SELF CASCODE CURRENT MIRROR}\par
A self cascode current mirror is proposed that required a low bias voltage of order of ± 1.0V \hyperref[b8]{[9,}\hyperref[b9]{10]}. The selection criterion for I 3 is to ensure lower V in . I 2 is selected to ensure ON condition for M6 (Fig: \hyperref[fig_5]{7}). The aspect ratios of different transistors are given in TABLE1. The small signal transfer analysis of this circuit at 20 ?A gave the current gain, i.e. Iout/ Iin = 1, and output resistance as 10 M?. The power dissipation for this is high. Simulation results for I out vs V ds curve for Self Cascode Current Mirror are shown in fig 8. This approach of increasing the (W/L) aspect ratios works Iref effectively at low bias voltage Vin of 1 V making it quite attractive for biasing analog circuits requiring high output resistance and gain. Hence they can be used as load resistances in CM circuits. They can extensively be used where power supply requirements are not the constraint.\par
Advantages:\par
1. High performance since output current is constant for low value of V ds . 2. High output impedance. 
\section[{Disadvantages:}]{Disadvantages:}\par
1. Power dissipation is high.    \begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Fig 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Fig 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-4.png}
\caption{\label{fig_2}2 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Fig 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Fig 5 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Fig 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{} \par 
\begin{longtable}{}
\end{longtable} \par
 
\caption{\label{tab_0}Table}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{} \par 
\begin{longtable}{}
\end{longtable} \par
  {\small\itshape [Note: 1 : aspect ratios of all MOSFETS Design specifications:]} 
\caption{\label{tab_1}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3} \par 
\begin{longtable}{P{0.85\textwidth}}
2011\\
September\\
63\end{longtable} \par
  {\small\itshape [Note: vs V curve for Low voltage self cascodeCurrent Mirror.]} 
\caption{\label{tab_2}Table 3 :}\end{figure}
 		 		\backmatter  			  				\begin{bibitemlist}{1}
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\bibitem[Rajput ()]{b8}\label{b8} 	 		\textit{Low voltage current mode circuit structures and their applications},  		 			S S Rajput 		.  		2002. Delhi.  		 			Indian Institute of Technology 		 	 	 (Ph.D. Thesis) 
\bibitem[Rincon and Gabriel (1995)]{b4}\label{b4} 	 		‘Low Voltage Design Techniques and Considerations for Integrated Operational Amplifier Circuit’.  		 			Alfonso Rincon 		,  		 			M Gabriel 		.  	 	 		\textit{Georgia Institute of Technology}  		May 31. 1995. 30332.  	 
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\bibitem[© 2011 Global Journals Inc. (US) out ds]{b11}\label{b11} 	 		\textit{© 2011 Global Journals Inc. (US) out ds},  				 	 
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\end{document}
